CDCM6208V1RGZT datasheet(35/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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ELF

R2

C2

C1

R3

C3

CDCM6208

www.ti.com

SCAS931A – MAY 2012 – REVISED JUNE 2012

PRESCALER DIVIDERS (PS_A, PS_B)

The prescaler (PS) dividers are fed by the output of the VCO and are distributed to the output dividers (PS_A to

the dividers for Outputs 0, 1, 4, and 5 and PS_B to the dividers for Outputs 2, 3, 6, and 7. PS_A also completes

the PLL as it also drives the input of the Feedback Divider (N).

PHASE FREQUENCY DETECTOR (PFD)

The PFD takes inputs from the Smart Input MUX output and the feedback divider output and produces an output

that is dependent on the phase and frequency difference between the two inputs. The allowable range of

frequencies at the inputs of the PFD is from 8 kHz to 100 MHz.

CHARGE PUMP (CP)

The charge pump is controlled by the PFD which dictates either to pump up or down in order to charge or

discharge the integrating section of the on-chip loop filter. The integrated and filtered charge pump current is then

converted to a voltage that drives the control voltage node of the internal VCO through the loop filter. The range

of the charge pump current is from 500 µA to 4 mA.

Programmable Loop Filter

The on-chip PLL supports a partially internal and partially external loop filter configuration for all PLL loop

bandwidths where the passive external components C1, C2, and R2 are connected to the ELF pin as shown in

Figure 34 to achieve PLL loop bandwidths from 400 kHz down to 10 Hz.

Figure 34. CDCM6208 PLL Loop Filter Topology

Loop filter Component Selection

The loop filter setting and external resistor selection is important to set the PLL to best possible bandwidth and to

minimize jitter. A high bandwidth (

≥ 100 kHz) provides best input signal tracking and is therefore desired with a

clean input reference (synthesizer mode). A low bandwidth (

≤ 1 kHz) is desired if the input signal quality is

unknown (jitter cleaner mode). TI provides a software tool that makes it easy to select the right loop filter

components. C1, R2, and C2 are external loop filter components, connected to the ELF pin. The 3 rd pole of the

loop filter is device internal with R3 and C3 register selectable.

Device output signaling

LVDS-like: All outputs Y[7:0] support LVDS-like signaling. The actual output stage uses a CML structure and

drives a signal swing identical to LVDS (~350mV). The output slew rate is faster than standard LVDS for best

jitter performance. The LVDS-like outputs should be AC-coupled when interfacing to a LVDS receiver. See

reference schematic Figure 56 for an example. The supply voltage for outputs configured LVDS can be selected

freely between 1.8 V and 3.3 V.

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