CDCM6208V1RGZT datasheet(34/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

Download	78 Pages

Scroll/Zoom	100%

Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

Logo

34 / 78 page

CDCM6208

SCAS931A – MAY 2012 – REVISED JUNE 2012

www.ti.com

Universal INPUT Buffer (PRI_REF, SEC_REF)

The universal input buffers support multiple signaling formats (LVDS, CML or LVCMOS) and these require

external termination schemes. The secondary input buffer also supports crystal inputs and Table 28 provides the

characteristics of the crystal that can be used. Both inputs incorporate hysteresis.

VCO CALIBRATION

The LC VCO is designed using high-Q monolithic inductors and has low phase noise characteristics. The VCO of

the CDCM6208 must be calibrated to ensure that the clock outputs deliver optimal phase noise performance.

Fundamentally, a VCO calibration establishes an optimal operating point within the tuning range of the VCO.

While transparent to the user, the CDCM6208 and the host system perform the following steps comprising a

VCO calibration sequence:

1. Normal Operation- When the CDCM6208 is in normal (operational) mode, the state of both the power down

pin (PDN) and reset pin (RESETN) is high.

2. Entering the reset state – If the user wishes to restore all device defaults and initiate a VCO calibration

sequence, then the host system must place the device in reset via the PDN pin, via the RESETN pin, or by

removing and restoring device power. Pulling either of these pins low places the device in the reset state.

Holding either pin low holds the device in reset.

3. Exiting the reset state – The device calibrates the VCO either by exiting the device reset state or through

the device reset command initiated via the host interface. Exiting the reset state occurs automatically after

power is applied and/or the system restores the state of the PDN or RESETN pins from the low to high state.

Exiting the reset state using this method causes the device defaults to be loaded/reloaded into the device

register bank. Invoking a device reset via the register bit does not restore device defaults; rather, the device

retains settings related to the current clock frequency plan. Using this method allows for a VCO calibration

for a frequency plan other than the default state (i.e. the device calibrates the VCO based on the settings

contained within the register bank at the time that the register bit is accessed). The nominal state of this bit is

low. Writing this bit to a high state and then returning it to the low state invokes a device reset without

restoring device defaults.

4. Device stabilization – After exiting the reset state as described in Step 3, the device monitors internal

voltages and starts a reset timer. Only after internal voltages are at the correct level and the reset time has

expired will the device initiate a VCO calibration. This ensures that the device power supplies and phase

locked loops have stabilized prior to calibrating the VCO.

5. VCO Calibration – The CDCM6208 calibrates the VCO. During the calibration routine, the device holds all

outputs in reset so that the CDCM6208 generates no spurious clock signals.

REFERENCE DIVIDER (R)

The reference (R) divider is a continuous 4-b counter (1 – 16) that is present on the primary input before the

Smart Input MUX. It is operational in the frequency range of 8 kHz to 250 MHz. The output of the R divider sets

the input frequency for the Smart MUX and the auto switch capability of the Smart MUX can then be employed

as long as the secondary input frequency is no more than ± 20% different from the output of the R divider.

INPUT DIVIDER (M)

The input (M) divider is a continuous 14-b counter (1 – 16384) that is present after the Smart Input MUX. It is

operational in the frequency range of 8 kHz to 250 MHz. The output of the M divider sets the PFD frequency to

the PLL and should be in the range of 8 kHz to 100 MHz.

FEEDBACK DIVIDER (N)

The feedback (N) divider is made up of cascaded 8-b counter divider (1 – 256) followed by a 10-b counter divider

(1 – 1024) that are present on the feedback path of the PLL. It is operational in the frequency range of 8 kHz to

800 MHz. The output of the N divider sets the PFD frequency to the PLL and should be in the range of 8 kHz to

100 MHz. The frequency out of the first divider is required to be less than or equal to 200 MHz to ensure proper

operation.

34

Submit Documentation Feedback

Product Folder Link(s): CDCM6208

Similar Part No. - CDCM6208V1RGZT

Manufacturer	Part #	Datasheet	Description
Texas Instruments	CDCM6208V1RGZT	2Mb / 92P	[Old version datasheet] 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers

More results

Similar Description - CDCM6208V1RGZT

Manufacturer	Part #	Datasheet	Description
Texas Instruments	CDCM6208V1F	2Mb / 87P	[Old version datasheet] 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
	CDCM6208	2Mb / 89P	[Old version datasheet] 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers
	CDCM6208	2Mb / 92P	[Old version datasheet] 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers
	CDCM6208V2G	2Mb / 88P	[Old version datasheet] CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
Analog Devices	AD9523	1,011Kb / 60P	Jitter Cleaner and Clock Generator
Analog Devices	AD9524	973Kb / 56P	Jitter Cleaner and Clock Generator
Texas Instruments	CDCE62002	1Mb / 49P	[Old version datasheet] Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
	LMK04100	588Kb / 46P	[Old version datasheet] Clock Jitter Cleaner with Cascaded PLLs
	LMK04100	1Mb / 52P	[Old version datasheet] Family Clock Jitter Cleaner
	CDCE62005	2Mb / 80P	[Old version datasheet] Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

More results

CDCM6208V1RGZT Datasheet(PDF) 34 Page - Texas Instruments

CDCM6208V1RGZT Datasheet(HTML) 34 Page - Texas Instruments

Similar Part No. - CDCM6208V1RGZT

Similar Description - CDCM6208V1RGZT

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Download

Link URL