CDCM6208V1RGZT datasheet(33/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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CDCM6208

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SCAS931A – MAY 2012 – REVISED JUNE 2012

INPUT MUX and SMART INPUT MUX

The Smart Input MUX supports auto-switching and manual-switching using control pin (and through register).

The Smart Input MUX is designed such that glitches created during switching in both auto and manual modes

are suppressed at the MUX output.

Table 7. Input Mux Selection

Register 4 bit

SI_MODE1

Register 4 bit 12

REF_SEL

13SMUX_MODE_SE

Selected input

Pin No. 47

SMUX_REF_SEL

Pin No. 6

L

Auto Select Priority is given to Primary

0

X

Reference input.

0

Primary input

input select through

1

0 (SPI/I2C mode)

SPI/I2C

1

Secondary input

1

0

Primary input

input select through

1

external pin

1

Secondary input

0

Primary or Auto (see Table 9)

1 (pin mode)

not available

1

Secondary or Auto (see Table 9)

Example 1:An application desired to auto-select the clock reference in SPI/I2C mode. During production testing

however, the system needs to force the device to use the primary followed by the secondary input. The settings

would be as follows:

1. Tie REF_SEL pin always high

2. For primary clock input testing, use R4[13:12] = 10

3. For secondary clock input testing, set R4[13:12] = 11.

4. For the auto-mux setting in the final product shipment, set R3[13:12]=01 or 00

Example 2: The application wants to select the clock input manually without programming SPI/I2C. In this case,

program R4[13:12] = 11, and select primary or secondary input by toggling REF_SEL low or high.

SmartMux input frequency limitation: In the automatic mode, the frequencies of both inputs to the smart mux

(PRI_REF divided by R and SEC_REF) need to be similar; however, they can vary by up to 20%.

Switching behavior: The phase of the input clocks can be any. When the switching happens between one input

clock to the other, the phase of the output clock slowly transitions to the phase of the newly selection input clock.

There will be no-phase jump at the output. The phase transition time to the new reference clock signal depends

on the PLL loop filter bandwidth. Auto-switch assigns higher priority to PRI_REF and lower priority to SEC_REF.

The timing diagram of an auto-switch at the input MUX is shown in Figure 33.

Figure 33. Smart Input MUX Auto-Switch Mode Timing Diagram

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