CDCM6208V1RGZT datasheet(29/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

Download	78 Pages

Scroll/Zoom	100%

Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

Logo

29 / 78 page

RESET=low

CDCM6208

Step 1

SPI or I2C

Master

GPO

Configure

Registers

0 to 21

CDCM6208

Step 2

SPI or I2C

Master

GPO

Release

RESET

50k

DVDD

RESET=high

50k

DVDD

Register

Space

Register

Space

CDCM6208

www.ti.com

SCAS931A – MAY 2012 – REVISED JUNE 2012

Figure 28. Reset Pin Control During Register Loading

POWER DOWN

When PDN pin = 1, the device functions in the normal operating mode. There is also a register bit which should

indicate that when PDN pin = 0, the device enters a complete power down mode or enters a standby mode

(normal device operation with lower power). When this register bit is set to 0 and PDN = 0, the device shuts

down completely with a current consumption of no more than 1mA from the entire device. When this register bit

is set to 1 and PDN = 0, the output MUX and the output buffer of one of the two outputs that share the same

integer divider (a total of two output MUX-es and two output buffers) are shut down.

Device Power up timing:

Before the device outputs turn on after power up, the device goes through the following initialization routine:

Table 6.

Step

Duration

Comments

Depends on customer supply

The POR monitor holds the device in power-down or reset until the

Step 1: Power up ramp

ramp time

VDD supply voltage reaches 1.06 V (min) to 1.26 V (max)

Depends on XTAL. Could be

This step assumes RESETN = 1 and PDN = 1.The XTAL startup

several ms;

time is the time it takes for the XTAL to oscillate with sufficient

Step 2: XO startup (if crystal is

For NX3225GA 25 MHz typical

amplitude. The CDCM6208 has a built-in amplitude detection circuit,

used)

XTAL startup time measures 200

and holds the device in reset until the XTAL stage has sufficient

µs.

swing.

This counter of 64 k clock cycles needs to expire before any further

power-up step is done inside the device. This counter ensures that

64k Reference clock cycles at

Step 3: Ref Clock Counter

the input to the PFD from PRI or SEC input has stabilized in

PFD input

frequency. The duration of this step can range from 640 µs (fPFD=

100 MHz) to 8 sec (8 kHz PFD).

64k FBCLK cycles with CW=32;

The duration is similar to Step 3,

or can be more accurately

The Feedback counter delays the startup by another 64k PFD clock

estimated as:

cycles. This is so that all counters are well initialized and also ensure

Step 4: FBCLK counter

V1: approximately 64k x PS_A x

additional timing margin for the reference clock to settle. This step

N/2.48 GHz

can range from 640 µs (fPFD= 100 MHz) to 8 sec (fPFD= 8kHz).

V2: approximately 64k x PS_A x

N/3.05 GHz

Submit Documentation Feedback

29

Product Folder Link(s): CDCM6208

Similar Part No. - CDCM6208V1RGZT

Manufacturer	Part #	Datasheet	Description
Texas Instruments	CDCM6208V1RGZT	2Mb / 92P	[Old version datasheet] 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers

More results

Similar Description - CDCM6208V1RGZT

Manufacturer	Part #	Datasheet	Description
Texas Instruments	CDCM6208V1F	2Mb / 87P	[Old version datasheet] 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
	CDCM6208	2Mb / 89P	[Old version datasheet] 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers
	CDCM6208	2Mb / 92P	[Old version datasheet] 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers
	CDCM6208V2G	2Mb / 88P	[Old version datasheet] CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
Analog Devices	AD9523	1,011Kb / 60P	Jitter Cleaner and Clock Generator
Analog Devices	AD9524	973Kb / 56P	Jitter Cleaner and Clock Generator
Texas Instruments	CDCE62002	1Mb / 49P	[Old version datasheet] Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs
	LMK04100	588Kb / 46P	[Old version datasheet] Clock Jitter Cleaner with Cascaded PLLs
	LMK04100	1Mb / 52P	[Old version datasheet] Family Clock Jitter Cleaner
	CDCE62005	2Mb / 80P	[Old version datasheet] Five/Ten Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

More results

CDCM6208V1RGZT Datasheet(PDF) 29 Page - Texas Instruments

CDCM6208V1RGZT Datasheet(HTML) 29 Page - Texas Instruments

Similar Part No. - CDCM6208V1RGZT

Similar Description - CDCM6208V1RGZT

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Download

Link URL