CDCM6208V1RGZT datasheet(3/78 Pages) TI

Part #	CDCM6208V1RGZT

Description	2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS

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Manufacturer	TI [Texas Instruments]

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10GbE

CDCM6208

Synthesizer

Mode

4x10G Ethernet ASIC

10G

PHY

10G

PHY

10G

PHY

10G

PHY

DDR

1G

PHY

PCIe

10G

PHY

DPLL

CDCM6208

www.ti.com

SCAS931A – MAY 2012 – REVISED JUNE 2012

Spurious Performance: The spurious performance is as follows:

•

Less than -80 dBc spurious from PFD/reference clocks at 122.88 MHz output frequency in the Nyquist range.

•

Less than -68 dBc spurious from output channel-to-channel coupling on the victim output at differential

signaling level operated at 122.88 MHz output frequency in the Nyquist range.

Device outputs:

The Device outputs offer multiple signaling formats: high-swing CML (LVPECL like), normal-swing CML (CML),

low-swing CML (LVDS like), HCSL, and LVCMOS signaling.

Table 3.

Outputs

LVPECL

CML

LVDS

HCSL

LVCMOS

Output Divider

Frequency range

Y[3:0]

X

Integer only

1.55 - 800 MHz

Integer

1.55 - 800 MHz

Y[7:4]

X

Fractional

1.00 - 400 MHz

Outputs [Y0:Y3] are driven by 8-b continuous integer dividers per pair. Outputs [Y4:Y7] are each driven by 20-b

fractional dividers that can achieve any frequency with better than 1ppm frequency accuracy. The output skew is

typically less than 40 ps for differential outputs. The LVCMOS outputs support adjustable slew rate control to

control EMI. Pairs of 2 outputs can be operated at 1.8 V, 2.5 V or 3.3 V power supply voltage.

Device Configuration:32 distinct pin modes are available that cover many common use cases without the need

for any serial programming of the device. For maximum flexibility the device also supports SPI and I2C

programming. I2C offers 4 distinct addresses to support up to 4 devices on the same programming lines.

Figure 1. Typical use case: CDCM6208 Example in Wireless Infrastructure Baseband Application

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