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AD9633 Datasheet(PDF) 30 Page - Analog Devices |
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AD9633 Datasheet(HTML) 30 Page - Analog Devices |
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30 / 40 page  AD9633 Data Sheet Rev. 0 | Page 30 of 40 Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. SDIO/OLM Pin For applications that do not require SPI mode operation, the CSB pin is tied to AVDD, and the SDIO/OLM pin controls the output lane mode according to Table 13. For applications where this pin is not used, CSB should be tied to AVDD. When using the one-lane mode, the encode rate should be ≤83.33 MSPS to meet the maximum output rate of 1 Gbps. Table 13. Output Lane Mode Pin Settings OLM Pin Voltage Output Mode AVDD (Default) Two-lane. 1× frame, 12-bit serial output GND One-lane. 1× frame, 12-bit serial output SCLK/DTP Pin The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device power- up. When SCLK/DTP is tied to AVDD, the ADC channel outputs shift out the following pattern: 1000 0000 0000. The FCO and DCO function normally while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output data. This pin has an internal 10 kΩ resistor to GND. It can be left unconnected. Table 14. Digital Test Pattern Pin Settings Selected DTP DTP Voltage Resulting D0±x and D1±x Normal Operation 10 kΩ to AGND Normal operation DTP AVDD 1000 0000 0000 Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section for information about the options available. CSB Pin The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. RBIAS Pin To set the internal core bias current of the ADC, place a 10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin. OUTPUT TEST MODES The output test options are described in Table 11 and controlled by the output test mode bits at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is discon- nected from the digital back-end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. |
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