 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD9633 Datasheet(PDF) 26 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9633 Datasheet(HTML) 26 Page - Analog Devices |
|
|
26 / 40 page  AD9633 Data Sheet Rev. 0 | Page 26 of 40 Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by ) 2 1 ( log 20 = 10 j A t f ation SNR Degrad × × π In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 67). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9633. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs. 1 10 100 1000 16 BITS 14 BITS 12 BITS 30 40 50 60 70 80 90 100 110 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps ANALOG INPUT FREQUENCY (MHz) 10 BITS 8 BITS RMS CLOCK JITTER REQUIREMENT Figure 67. Ideal SNR vs. Input Frequency and Jitter POWER DISSIPATION AND POWER-DOWN MODE As shown in Figure 68, the power dissipated by the AD9633 is proportional to its sample rate. The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. 350 300 250 200 150 100 10 130 SAMPLE RATE (MSPS) 20 30 40 50 60 70 80 90 100 110 120 50 MSPS 80 MSPS 105 MSPS 125 MSPS 40 MSPS 20 MSPS 65 MSPS Figure 68. Analog Core Power vs. fSAMPLE for fIN = 10.3 MHz The AD9633 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates 2 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9633 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering power- down mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map section for more details on using these features. |
Similar Part No. - AD9633 |
|
Similar Description - AD9633 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
