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AD9633 Datasheet(PDF) 6 Page - Analog Devices

Part # AD9633
Description  Quad, 12-Bit, 80 MSPS/105 MSPS
Download  40 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9633 Datasheet(HTML) 6 Page - Analog Devices

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AD9633
Data Sheet
Rev. 0 | Page 6 of 40
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2
Temp
Min
Typ
Max
Unit
CLOCK3
Input Clock Rate
Full
10
1000
MHz
Conversion Rate
Full
10
80/105/125
MSPS
Clock Pulse Width High (tEH)
Full
6.25/4.76/4.00
ns
Clock Pulse Width Low (tEL)
Full
6.25/4.76/4.00
ns
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Full
2.3
ns
Rise Time (tR) (20% to 80%)
Full
300
ps
Fall Time (tF) (20% to 80%)
Full
300
ps
FCO Propagation Delay (tFCO)
Full
1.5
2.3
3.1
ns
DCO Propagation Delay (tCPD)4
Full
tFCO + (tSAMPLE/12)
ns
DCO to Data Delay (tDATA)4
Full
(tSAMPLE/12) − 300
(tSAMPLE/12)
(tSAMPLE/12) + 300
ps
DCO to FCO Delay (tFRAME)4
Full
(tSAMPLE/12) − 300
(tSAMPLE/12)
(tSAMPLE/12) + 300
ps
Lane Delay (tLD)
90
ps
Data to Data Skew (tDATA-MAX − tDATA-MIN)
Full
±50
±200
ps
Wake-Up Time (Standby)
25°C
250
ns
Wake-Up Time (Power-Down)5
25°C
375
μs
Pipeline Latency
Full
16
Clock cycles
APERTURE
Aperture Delay (tA)
25°C
1
ns
Aperture Uncertainty (Jitter, tJ)
25°C
1
35
fs rms
Out-of-Range Recovery Time
25°C
1
Clock cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured on standard FR-4 material.
3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.
4 tSAMPLE/12 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS.
5 Wake-up time is defined as the time required to return to normal operation from power-down mode.


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