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CLRC663 Datasheet(PDF) 99 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 99 Page - NXP Semiconductors |
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99 / 132 page  CLRC663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.3 — 3 April 2012 171133 99 of 132 NXP Semiconductors CLRC663 Contactless reader IC 9.14 Low-power card detection configuration registers The LPCD registers contain the settings for the low-power card detection. The setting for LPCD_IMax (6 bits) is done by the two highest bits (bit 7, bit 6) of the registers LPCD_QMin, LPCD_QMax and LPCD_IMin each. 9.14.1 LPCD_QMin Table 175. PLLDiv_Out bits Bit Symbol Description 7 to 0 PLLDiv_Out PLL output divider factor; Refer to Section 8.8.2 Table 176. Setting for the output divider ratio PLLDiv_Out [7:0] Value Division 0RFU 1RFU 2RFU 3RFU 4RFU 5RFU 6RFU 7RFU 88 99 10 10 ... ... 253 253 254 254 Table 177. LPCD_QMin register (address 3Fh) Bit 7 6 5 4 3 2 1 0 Symbol LPCD_IMax.5 LPCD_IMax.4 LPCD_QMin Access rights r/w r/w r/w Table 178. LPCD_QMin bits Bit Symbol Description 7, 6 LPCD_IMax Defines the highest two bits of the higher border for the LPCD. If the measurement value of the I channel is higher than LPCD_IMax, a LPCD interrupt request is indicated by bit IRQ0.LPCDIrq 5 to 0 LPCD_QMin Defines the lower border for the LPCD. If the measurement value of the Q channel is higher than LPCD_QMin, a LPCDinterrupt request is indicated by bit IRQ0.LPCDIrq |
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