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CLRC663 Datasheet(PDF) 7 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 132 page  CLRC663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.3 — 3 April 2012 171133 7 of 132 NXP Semiconductors CLRC663 Contactless reader IC 8.1 Interrupt controller The interrupt controller handles the enabling/disabling of interrupt requests. All of the interrupts can be configured by firmware. Additionally, the firmware has possibilities to trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0 and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt controller registers is implemented. The CLRC663 indicates certain events by setting bit IRQ in the register Status1Reg and additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. The following table shows the available interrupt bits, the corresponding source and the condition for its activation. The interrupt bit TimernIrq in register IRQ1 indicates an interrupt set by the timer unit. The setting is done if the timer underflows. The TxIrq bit in register IRq0 indicates that the transmission is finished. If the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit sets the interrupt bit automatically. The bit RxIrq in register IRQ0 indicates an interrupt when the end of the received data is detected. The bit IdleIrq in register IRQ0 is set if a command finishes and the content of the command register changes to idle. The waterlevel defines both - minimum and maximum warning levels - counting from top and from bottom of the FIFO by a single value. The bit HiAlertIrq in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that means the FIFO data number has reached the top level as configured by the bit WaterLevel. The bit LoAlertIrq in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that means the FIFO data number has reached the bottom level as configured by the bit WaterLevel. The bit ErrIrq in register IRQ0 indicates an error detected by the contactless UART during receive. This is indicated by any bit set to logic 1 in register Error. The bit LPCDIrq in register IRQ0 indicates a card detected. The bit RxSOFIrq in register IRQ0 indicates a detection of a SOF or a subcarrier by the contactless UART during receiving. The bit GlobalIRq in register IRQ1 indicates an interrupt occurring at any other interrupt source when enabled. |
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