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CLRC663 Datasheet(PDF) 45 Page - NXP Semiconductors |
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CLRC663 Datasheet(HTML) 45 Page - NXP Semiconductors |
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45 / 132 page  CLRC663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.3 — 3 April 2012 171133 45 of 132 NXP Semiconductors CLRC663 Contactless reader IC 8.6.5 Symbol generator The symbol generator is used to create various protocol symbols. These can be e.g. SOF or EOF symbols as they are used by the ISO14443 protocols or proprietary protocol symbols like the CS symbol as used by the ICODE EPC protocol. Symbols are defined by means of the symbol definition registers and the mode registers. Four different symbols can be used. Two of them, Symbol0 and Symbol1 have a maximum pattern length of 16 bit and feature a burst length of up to 256 bits of either logic “0” or logic “1”. The Symbol2 and Symbol3 are limited to 8 bit pattern length and do not support a burst. The definition of symbol patterns is done by writing the bit sequence of the pattern to the appropriate register. The last bit of the pattern to be sent is located at the LSB of the register. By setting the symbol length in the symbol-length register (TxSym10Len and TxSym32Len) the definition of the symbol pattern is completed. All other bits at bit-position higher than the symbol length in the definition register are ignored. (Example: length of Symbol2 = 5, bit7 and bit6 are ignored, bit5 to bit0 define the symbol pattern, bit5 is sent first) Which symbol-pattern is sent can be configured in the TxFrameCon register. Symbol0, Symbol1 and Symbol2 can be sent before data packets, Symbol1, Symbol2 and Symbol3 can be sent after data packets. Each symbol is defined by a set of registers. Symbols are configured by a pair of registers. Symbol0 and Symbol1 share the same configuration and Symbol2 and Symbol3 share the same configuration. The configuration includes setting of bit-clock- and subcarrier-frequency, as well as selection of the pulse type/length and the envelope type. 8.7 Memory 8.7.1 Memory overview The CLRC663 implements three different memories: EEPROM, FIFO and Registers. At startup, the initialization of the registers which define the behavior of the IC is performed by an automatic copy of an EEPROM area (read/write EEPROM section1 and section2, register reset) into the registers. The behavior of the CLRC663 can be changed by executing the command LoadProtocol, which copies a selected default protocol from the EEPROM (read only EEPROM section4, register Set Protocol area) into the registers. The read/write EEPROM section2 can be used to store any user data or predefined register settings. These predefined settings can be copied with the command "LoadRegister" into the internal registers. The FIFO is used as Input/Out buffer and is able to improve the performance of a system with limited interface speed. |
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