1617—08/19/09

ICS9EMS9633

ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS

5

Datasheet

MLF Pin Description

PIN #

PIN NAME

TYPE

DESCRIPTION

1

CPU_STOP#

IN

Stops all CPU clocks, except those set to be free running clocks

2

CLKPWRGD#/PD_3.3

IN

This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs

are valid and are ready to be sampled. This is an active low input. / Asynchronous

active high input pin used to place the device into a power down state.

3X2

OUT

Crystal output, Nominally 14.318MHz

4

X1

IN

Crystal input, Nominally 14.318MHz.

5

VDDREF_3.3

PWR Power pin for the XTAL and REF clocks, nominal 3.3V

6

REF

OUT

14.318 MHz reference clock.

7

GNDREF

PWR Ground pin for the REF outputs.

8

VDDCORE_3.3

PWR 3.3V power for the PLL core

9FSC_L

IN

Low threshold input for CPU frequency selection. Refer to input electrical

characteristics for Vil_FS and Vih_FS values.

10

TEST_MODE

IN

TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode

while in test mode. Refer to Test Clarification Table.

11

TEST_SEL

IN

TEST_SEL: latched input to select TEST MODE

1 = All outputs are tri-stated for test

0 = All outputs behave normally.

12

SCLK_3.3

IN

Clock pin of SMBus circuitry, 3.3V tolerant.

13

SDATA_3.3

I/O

Data pin for SMBus circuitry, 3.3V tolerant.

14

VDDCORE_3.3

PWR 3.3V power for the PLL core

15

VDDIO_1.5

PWR Power supply for low power differential outputs, nominal 1.5V.

16

DOT96C_LPR

OUT

Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm

resistor to GND needed. No Rs needed.

17

DOT96T_LPR

OUT

True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor

to GND needed. No Rs needed.

18

GNDDOT

PWR Ground pin for DOT clock output

19

GNDLCD

PWR Ground pin for LCD clock output

20

LCD100C_LPR

OUT

Complement clock of low power differential pair for LCD100 SS clock. No 50ohm

resistor to GND needed. No Rs needed.

21

LCD100T_LPR

OUT

True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to

GND needed. No Rs needed.

22

VDDIO_1.5

PWR Power supply for low power differential outputs, nominal 1.5V.

23

VDDCORE_3.3

PWR 3.3V power for the PLL core

24

*CR#0

IN

Clock request for SRC0, 0 = enable, 1 = disable