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IDT82P20516BFBLANK Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT82P20516BFBLANK Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 115 page  IDT82P20516 16-CHANNEL SHORT HAUL E1 LINE INTERFACE UNIT Table of Contents 4 December 17, 2009 3.5.1.1 Bipolar Violation (BPV) / Code Violation (CV) Detection ............................................................. 31 3.5.1.2 Bipolar Violation (BPV) Insertion ................................................................................................. 31 3.5.2 Excessive Zeroes (EXZ) Detection ............................................................................................................. 31 3.5.3 Loss of Signal (LOS) Detection ................................................................................................................... 32 3.5.3.1 Line LOS (LLOS) ......................................................................................................................... 32 3.5.3.2 System LOS (SLOS) ................................................................................................................... 33 3.5.3.3 Transmit LOS (TLOS) ................................................................................................................. 34 3.5.4 Alarm Indication Signal (AIS) Detection and Generation ............................................................................ 35 3.5.4.1 Alarm Indication Signal (AIS) Detection ...................................................................................... 35 3.5.4.2 (Alarm Indication Signal) AIS Generation ................................................................................... 35 3.5.5 PRBS, QRSS, ARB and IB Pattern Generation and Detection ................................................................... 36 3.5.5.1 Pattern Generation ...................................................................................................................... 36 3.5.5.2 Pattern Detection ........................................................................................................................ 37 3.5.6 Error Counter .............................................................................................................................................. 38 3.5.6.1 Automatic Error Counter Updating .............................................................................................. 38 3.5.6.2 Manual Error Counter Updating .................................................................................................. 39 3.5.7 Loopback .................................................................................................................................................... 40 3.5.7.1 Analog Loopback ........................................................................................................................ 40 3.5.7.2 Remote Loopback ....................................................................................................................... 41 3.5.7.3 Digital Loopback .......................................................................................................................... 42 3.5.8 Channel 0 Monitoring .................................................................................................................................. 43 3.5.8.1 G.772 Monitoring ......................................................................................................................... 43 3.5.8.2 Jitter Measurement (JM) ............................................................................................................. 44 3.6 CLOCK INPUTS AND OUTPUTS ............................................................................................................................ 45 3.6.1 Free Running Clock Outputs on CLKE1 ..................................................................................................... 45 3.6.2 MCLK, Master Clock Input .......................................................................................................................... 46 3.6.3 XCLK, Internal Reference Clock Input ........................................................................................................ 46 3.7 INTERRUPT SUMMARY ......................................................................................................................................... 47 4 MISCELLANEOUS .......................................................................................................................................................... 49 4.1 RESET ..................................................................................................................................................................... 49 4.1.1 Power-On Reset ......................................................................................................................................... 50 4.1.2 Hardware Reset .......................................................................................................................................... 50 4.1.3 Global Software Reset ................................................................................................................................ 50 4.1.4 Per-Channel Software Reset ...................................................................................................................... 50 4.2 MICROPROCESSOR INTERFACE ......................................................................................................................... 50 4.3 POWER UP .............................................................................................................................................................. 51 4.4 HITLESS PROTECTION SWITCHING (HPS) SUMMARY ...................................................................................... 51 5 PROGRAMMING INFORMATION ................................................................................................................................... 54 5.1 REGISTER MAP ...................................................................................................................................................... 54 5.1.1 Global Register ........................................................................................................................................... 54 5.1.2 Per-Channel Register ................................................................................................................................. 55 5.2 REGISTER DESCRIPTION ..................................................................................................................................... 58 5.2.1 Global Register ........................................................................................................................................... 58 5.2.2 Per-Channel Register ................................................................................................................................. 62 |
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