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W9412G2IB Datasheet(PDF) 27 Page - Winbond |
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W9412G2IB Datasheet(HTML) 27 Page - Winbond |
27 / 50 page ![]() W9412G2IB Publication Release Date: Aug. 30, 2010 - 27 - Revision A06 9.5 DC Characteristics MAX. SYM. PARAMETER -4 -5/-5I -6/-6I UNIT NOTES IDD0 Operating current: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle 160 150 140 mA 7 IDD1 Operating current: One Bank Active-Read-Precharge; Burst = 2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once per clock cycle. 180 170 160 mA 7, 9 IDD2P Precharge Power Down standby current: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM 30 30 30 mA IDD2N Idle standby current: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM 45 45 45 mA 7 IDD3P Active Power Down standby current: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min 30 30 30 mA IDD3N Active standby current: CS > VIH min; CKE > VIH min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle 60 60 60 mA 7 IDD4R Operating current: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=3; tCK = tCK min; IOUT = 0mA 240 220 200 mA 7, 9 IDD4W Operating current: Burst = 2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle 270 250 230 mA 7 IDD5 Auto Refresh current: tRC = tRFC min 210 200 190 mA 7 IDD6 Self Refresh current: CKE < 0.2V 3 3 3 mA IDD7 Random Read current: 4 Banks Active Read with activate every 20nS, Auto-Precharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle 340 320 300 mA |
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