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W9412G2IB Datasheet(PDF) 17 Page - Winbond |
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W9412G2IB Datasheet(HTML) 17 Page - Winbond |
17 / 50 page ![]() W9412G2IB Publication Release Date: Aug. 30, 2010 - 17 - Revision A06 • Addressing Sequence of Interleave Mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. Address Sequence for Interleave Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 words Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 4 words Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 8 words Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 7.10.3 CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depend on the frequency of CLK. A6 A5 A4 CAS LATENCY 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved 7.10.4 DLL Reset bit (A8) This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset. 7.10.5 Mode Register /Extended Mode register change bits (BA0, BA1) These bits are used to select MRS/EMRS. BA1 BA0 A11 −A0 0 0 Regular MRS Cycle 0 1 Extended MRS Cycle 1 x Reserved |
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