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W9412G2IB Datasheet(PDF) 4 Page - Winbond |
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W9412G2IB Datasheet(HTML) 4 Page - Winbond |
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4 / 50 page  W9412G2IB Publication Release Date: Aug. 30, 2010 - 4 - Revision A06 1. GENERAL DESCRIPTION W9412G2IB is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM); organized as 1,048,576 words × 4 banks × 32 bits. W9412G2IB delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the personal computer industrial standard, W9412G2IB is sorted into following speed grades: -4, -5, -5I, -6 and -6I. The -4 is compliant to the DDR500/CL3 or CL4 specification. The -5/-5I is compliant to the DDR400/CL3 specification (-5I grade which is guaranteed to support -40°C ~ 85°C). The -6/-6I is compliant to the DDR333/CL2.5 specification (-6I grade which is guaranteed to support -40°C ~ 85°C). All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. Write and Read data are synchronized with the both edges of DQS (Data Strobe). By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9412G2IB is ideal for any high performance applications. 2. FEATURES • 2.5V ±0.2V Power Supply for DDR 333/400 • 2.5V ±0.1V Power Supply for DDR500 • Up to 250 MHz Clock Frequency • Double Data Rate architecture; two data transfers per clock cycle • Differential clock inputs (CLK and CLK ) • DQS is edge-aligned with data for Read; center-aligned with data for Write • CAS Latency: 2, 2.5, 3 and 4 • Burst Length: 2, 4 and 8 • Auto Refresh and Self Refresh • Precharged Power Down and Active Power Down • Write Data Mask • Write Latency = 1 • 15.6µS Refresh interval (4K/64 mS Refresh) • Maximum burst refresh cycle: 8 • Interface: SSTL_2 • Packaged in 144L LFBGA, using Lead free materials with RoHS compliant |
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