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GS9092A Datasheet(PDF) 29 Page - Gennum Corporation |
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GS9092A Datasheet(HTML) 29 Page - Gennum Corporation |
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29 / 63 page  GS9092A GenLINX® III 270Mb/s Serializer for SDI and DVB-ASI Data Sheet 34715 - 4 May 2010 29 of 63 Gating the WR_CLK Using the FIFO_FULL Flag Using the asynchronous FIFO_FULL flag to gate the WR_CLK requires external clock gating circuitry to generate a clean burst clock (see Figure 3-4). An example circuit for this application is shown in Figure 3-5. Figure 3-4: Burst Clock Figure 3-5: Example Circuit to Gate WR_CLK Using the FIFO_FULL Flag CORRECT INCORRECT FIFO_FULL Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D WR_CLK GATED WR_CLK FIFO_FULL GATED WR_CLK WR_CLK |
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Similar Description - GS9092A |
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