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GS9092A Datasheet(PDF) 27 Page - Gennum Corporation

Part # GS9092A
Description  GenLINX III 270Mb/s Serializer for SDI and DVB-ASI
Download  63 Pages
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Manufacturer  GENNUM [Gennum Corporation]
Direct Link  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS9092A Datasheet(HTML) 27 Page - Gennum Corporation

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GS9092A GenLINX® III 270Mb/s Serializer for SDI and
DVB-ASI
Data Sheet
34715 - 4
May 2010
27 of 63
3.3.2 DVB-ASI Mode
The internal FIFO is in DVB-ASI mode when the application layer sets the FIFO_EN pin
HIGH and the FIFO_MODE[1:0] bits in the IOPROC_DISABLE register are configured to
01b. By default, the FIFO_MODE[1:0] bits are set to 01b by the device whenever the
DVB_ASI pin is set HIGH (i.e. the device is in DVB-ASI mode); however, the application
layer may program the FIFO_MODE[1:0] bits as required.
Figure 3-3 shows the input and output signals of the FIFO when it is configured for
DVB-ASI Mode.
Figure 3-3: FIFO in DVB-ASI Mode
When operating in DVB-ASI mode, the GS9092A's FIFO can be used for clock rate
interchange operation. 8-bit MPEG data as well as a K_IN control signal must be written
to the FIFO by the application layer. The MPEG data and control signal can be
simultaneously clocked into the FIFO at any rate using the rising edge of the WR_CLK
pin.
The 8-bit MPEG data stream may consist of only MPEG packets, or both MPEG packets
and special characters (such as the K28.5 stuffing characters). The application layer must
set K_IN HIGH whenever a special character is present in the data stream, otherwise it
should be LOW. The GS9092A uses the K_IN signal to determine whether or not a given
byte in the FIFO is an MPEG packet that needs 8b/10b encoded.
The INSSYNCIN pin should be grounded while operating the FIFO in DVB-ASI mode.
The GS9092A internally reads the data out of the FIFO at the PCLK rate and adds the
necessary number of stuffing characters based on the FIFO status flags.
3.3.2.1 FIFO Status Flags
The FIFO contains internal read and write pointers used to designate which spot in the
FIFO the MPEG data will be read from or written to. These internal pointers control the
status flags FIFO_FULL and FIFO_EMPTY, which are available for output on the
multi-function I/O pins if so programmed (see Programmable Multi-function I/O on
page 51).
In the case where the write pointer is originally ahead of the read pointer, the
FIFO_EMPTY flag will be set HIGH when both pointers arrive at the same address (see
WR_CLK
K_IN
FIFO
(DVB-ASI Mode)
RD_CLK (PCLK)
Internal
Application Interface
8-bit MPEG Data
FIFO_FULL
FIFO_EMPTY
8-bit MPEG Data
K_IN


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