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GS9092A Datasheet(PDF) 56 Page - Gennum Corporation |
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GS9092A Datasheet(HTML) 56 Page - Gennum Corporation |
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56 / 63 page  GS9092A GenLINX® III 270Mb/s Serializer for SDI and DVB-ASI Data Sheet 34715 - 4 May 2010 56 of 63 Figure 3-16: GSPI Write Mode Timing 3.13.3 Configuration and Status Registers Table 3-14 summarizes the GS9092A's internal status and configuration registers. All of these registers are available to the host via the GSPI and are all individually addressable. Where status registers contain less than the full 16 bits of information, two or more registers may be combined at a single logical address. t3 SCLK CS SDIN SDOUT t0 t1 t2 t4 R/W RSV RSV AutoInc A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R/W RSV RSV AutoInc A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 t7 t8 Table 3-14: GS9092A Internal Registers Address Register Name Reference 00h IOPROC_DISABLE Section 3.7.3 02h EDH_FLAG Section 3.7.3.3 04h VIDEO_STANDARD Section 3.7.2 05h IO_CONFIG Section 3.11 06h FIFO_EMPTY_OFFSET Section 3.3.2.1 07h FIFO_FULL_OFFSET Section 3.3.2.1 08h - 09h ANC_LINE Section 3.3.3 0Fh - 10h VIDEO_FORMAT Section 3.7.3.1 11h - 14h RASTER_STRUCTURE Section 3.7.2 15h - 24h EDH_CALC_RANGES Section 3.7.3.3 26h - 27h 352M_LINE Section 3.7.3.1 28h ANC_WORDS Section 3.3.3 02Ch - 42Bh INTERNAL FIFO Section 3.3.3 |
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