 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
GS9090B Datasheet(PDF) 8 Page - Gennum Corporation |
|
|
|||||||||||||||||||||||||||||
GS9090B Datasheet(HTML) 8 Page - Gennum Corporation |
|
|
8 / 72 page  GS9090B GenLINX® III 270Mb/s Deserializer for SDI Data Sheet 40749 - 5 May 2010 8 of 72 20 SDIN_TDI Synchronous with SCLK_TCK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Serial Data Input / Test Data Input Host Mode (JTAG/HOST = LOW): SDIN_TDI operates as the host interface serial input, SDIN, used to write address and configuration information to the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH): SDIN_TDI operates as the JTAG test data input, TDI. 21, 29, 43 IO_VDD Non Synchronous Input Power Power supply for digital I/O. For a 3.3V tolerant I/O, connect pins to either +1.8V DC or +3.3V DC. For a 5V tolerant I/O, connect pins to a +3.3V DC. NOTE: For power sequencing requirements please see Device Power Up on page 64. 22 DATA_ERROR Synchronous with PCLK Output STATUS SIGNAL OUTPUT. Signal levels are LVCMOS / LVTTL compatible. The DATA_ERROR signal will be LOW when an error within the received data stream has been detected by the device. This pin is an inverted logical ‘OR’ing of all detectable errors listed in the internal ERROR_STATUS register. Once an error is detected, DATA_ERROR will remain LOW until the start of the next video frame / field, or until the ERROR_STATUS register is read via the host interface. The DATA_ERROR signal will be HIGH when the received data stream has been detected without error. NOTE: It is possible to program which error conditions are monitored by the device by setting appropriate bits in the ERROR_MASK register HIGH. All error conditions are detected by default. 23, 25, 26, 27 STAT[0:3] Synchronous with PCLK or RD_CLK Output MULTI FUNCTION I/O PORT Signal levels are LVCMOS / LVTTL compatible. Programmable multi-function outputs. By programming the bits is the IO_CONFIG register, each pin can output one of the following signals: •H •V •F •FIFO_LD • ANC_DETECT • EDH_DETECT • FIFO_FULL • FIFO_EMPTY These pins are set to certain default values depending on the configuration of the device and the internal FIFO mode selected. See Programmable Multi-Function Outputs on page 56 for details. 24, 28, 42 IO_GND Non Synchronous Input Power Ground connection for digital I/O. Connect to GND. Table 1-1: Pin List and Description (Continued) |
Similar Part No. - GS9090B |
|
Similar Description - GS9090B |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
