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ADC1613D Datasheet(PDF) 31 Page - NXP Semiconductors

Part # ADC1613D
Description  Dual 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

ADC1613D Datasheet(HTML) 31 Page - NXP Semiconductors

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ADC1613D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 9 February 2011
31 of 43
NXP Semiconductors
ADC1613D series
Dual 16-bit ADC: serial JESD204A interface
[1]
F: Octets per frame clock cycle
HD: High-density mode
K: Frame per multi-frame
M: Converters per device
L: Lane per converter device
CS: Number of control bits per conversion sample
CF: Control words per frame clock cycle and link
S: Number of samples transmitted per single converter per frame cycle
Table 28.
SER_Cfg_Setup (address 0803h)
Default values are highlighted.
Bit
Symbol
Access Value
Description
7 to 4 -
-
0000
not used
3 to 0 CFG_SETUP[3:0]
R/W
1000
quick configuration of JESD204A. These settings overrule the
configuration of pins CFG3 to CFG0 (see Table 29).
Table 29.
JESD204A configuration table
CFG_SETUP[3:0] ADC A
ADC B
Lane 0
Lane 1
F[1]
HD[1] K[1] M[1] L[1]
Comment
CS[1] CF[1] S[1]
0
0000
ON
ON
ON
ON
20
9
2
2
(F
× K) ≥ 17
0
0
1
1
0001
ON
ON
ON
OFF
4
0
5
2
1
(F
× K) ≥ 17
0
0
1
2
0010
ON
ON
OFF
ON
40
5
2
1
(F
× K) ≥ 17
0
0
1
30011
ON
OFF
ON
ON
11
17
1
2
(F
× K) ≥ 17
0
0
1
4
0100
OFF
ON
ON
ON
11
17
1
2
(F
× K) ≥ 17
0
0
1
5
0101
ON
OFF
ON
OFF
2
0
9
1
1
(F
× K) ≥ 17
0
0
1
60110
ON
OFF
OFF
ON
20
9
1
1
(F
× K) ≥ 17
0
0
1
7
0111
OFF
ON
ON
OFF
2
0
9
1
1
(F
× K) ≥ 17
0
0
1
8
1000
OFF
ON
OFF
ON
20
9
1
1
(F
× K) ≥ 17
0
0
1
9
1001
reserved
10
1010
reserved
11
1011
reserved
12
1100
reserved
13
1101
reserved
14
1110
ON
ON
ON
ON
2
0
9
2
2
test: loop
alignment
00
1
15
1111
OFF
OFF
OFF
OFF
2
0
9
2
2
chip
power-down
00
1


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