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Table 17.

Register allocation map

Address

(hex)

Register name

Access[1]

Bit definition

Default

(bin)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADC control register

0003

Channel index

R/W

-

-

-

-

-

-

ADCB

ADCA

1111 1111

0005

Reset and

Power-down

modes

R/W

SW_RST

-

-

-

-

-

PD[1:0]

0000 0000

0006

Clock

R/W

-

-

-

SE_SEL

DIFF_SE

-

CLKDIV2_SEL

DCS_EN

0000 0001

0008

Vref

R/W

-

-

-

-

INTREF_EN

INTREF[2:0]

0000 0000

0013

Offset

R/W

-

-

DIG_OFFSET[5:0]

0000 0000

0014

Test pattern 1

R/W

-

-

-

-

-

TESTPAT_1[2:0]

0000 0000

0015

Test pattern 2

R/W

TESTPAT_2[15:8]

0000 0000

0016

Test pattern 3

R/W

TESTPAT_3[7:0]

0000 0000

JESD204A control

0801

Ser_Status

R

RXSYNC_

ERROR

RESERVED[2:0]

0

0

POR_TST

RESERVED 0111 0000

0802

Ser_Reset

R/W

SW_RST

0

0

0

FSM_SW_

RST

0

0

0

0000 0000

0803

Ser_Cfg_Setup

R/W

0

0

0

0

CFG_SETUP[3:0]

0000 1000

0805

Ser_Control1

R/W

0

TRISTATE_

CFG_PINS

SYNC_

POL

SYNC_

SINGLE_

ENDED

1

REV_

SCR

REV_

ENCODER

REV_

SERIAL

0100 1001

0806

Ser_Control2

R/W

0

0

0

0

0

0

SWAP_

LANE_0_1

SWAP_

ADC_A_B

0000 0011

0808

Ser_Analog_Ctrl

R/W

0

0

0

0

0

SWING_SEL[2:0]

0000 0011

0809

Ser_ScramblerA

R/W

0

LSB_INIT[6:0]

0000 0000

080A

Ser_ScramblerB

R/W

MSB_INIT[7:0]

1111 1111

080B

Ser_PRBS_Ctrl

R/W

0

0

0

0

0

0

PRBS_TYPE[1:0]

0000 0000

0820

Cfg_0_DID

R*

DID[7:0]

1110 1101

0821

Cfg_1_BID

R/W*

0

0

0

0

BID[3:0]

0000 1010

0822

Cfg_3_SCR_L

R/W*

SCR

0

0

0

0

0

0

L

0000 0000

0823

Cfg_4_F

R/W*

0

0

0

0

0

F[2:0]

0000 0001

0824

Cfg_5_K

R/W*

0

0

0

K[4:0]

0000 1000

0825

Cfg_6_M

R/W*

0

0

0

0

0

0

0

M

0000 0000