ADC1613D_11 datasheet(22/43 Pages) NXP

Part #	ADC1613D

Description	Dual 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface

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Manufacturer	NXP [NXP Semiconductors]

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ADC1613D_SER

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Product data sheet

Rev. 3 — 9 February 2011

22 of 43

NXP Semiconductors

ADC1613D series

Dual 16-bit ADC: serial JESD204A interface

11.5 JESD204A serializer

For more information about the JESD204A standard refer to the JEDEC web site.

11.5.1 Digital JESD204A formatter

The block placed after the ADC cores is used to implement all functionalities of the

JESD204A standard. This ensures signal integrity and guarantees the clock and the data

recovery at the receiver side.

The block is highly parameterized and can be configured in various ways depending on

the sampling frequency and the number of lanes used.

Fig 20. CML output connection to the receiver (AC-coupled)

CMLPA/CMLPB

CMLNA/CMLNB

12 mA to 26 mA

100

Ω

50

Ω

10 nF

005aaa083

VDDD

−

+

RECEIVER

Fig 21. General overview of the JESD204A serializer

FRAME

TO

OCTETS

F octets

SCRAMBLER

TX transport layer

CF: position of control bits

HD: frame boundary break

Padding with Tail bits (TT)

Mx(N'xS) bits

Lx(F) octets

L octets

N' = N+CS

S samples per frame cycle

samples stream to

lane stream mapping

N bits from Cr0 +

CS bits for control

N bits from CrM−1 +

CS bits for control

M CONVERTERS

L LANES

LANE 1

FRAME

TO

OCTETS

F octets

SCRAMBLER

8-bit/

10-bit

SER

TX CONTROLLER

LANE 0

8-bit/

10-bit

SER

ALIGNMENT

CHARACTER

GENERATOR

ALIGNMENT

CHARACTER

GENERATOR

SYNC~

005aaa084

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ADC1613D Datasheet(PDF) 22 Page - NXP Semiconductors

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