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ADC1613D Datasheet(PDF) 20 Page - NXP Semiconductors |
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ADC1613D Datasheet(HTML) 20 Page - NXP Semiconductors |
20 / 43 page ![]() ADC1613D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 February 2011 20 of 43 NXP Semiconductors ADC1613D series Dual 16-bit ADC: serial JESD204A interface 11.3.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode voltage of the differential input stage is set via 5 k Ω internal resistors. a. Sine clock input b. Sine clock input (with transformer) c. LVPECL clock input Fig 17. Differential clock input Sine clock input CLKP CLKM 005aaa173 Sine clock input CLKP CLKM 005aaa054 LVPECL clock input 005aaa172 CLKP CLKM Vcm(clk) = common-mode voltage of the differential input stage. Fig 18. Equivalent input circuit CLKP CLKM 005aaa081 5 k Ω 5 k Ω Vcm(clk) SE_SEL SE_SEL package ESD parasitics |
Similar Part No. - ADC1613D_11 |
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Similar Description - ADC1613D_11 |
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