ADC1613D_11 datasheet(19/43 Pages) NXP

Part #	ADC1613D

Description	Dual 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface

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Manufacturer	NXP [NXP Semiconductors]

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ADC1613D_SER

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Product data sheet

Rev. 3 — 9 February 2011

19 of 43

NXP Semiconductors

ADC1613D series

Dual 16-bit ADC: serial JESD204A interface

11.2.3 Common-mode output voltage (VO(cm))

An 0.1

μF filter capacitor should be connected between the pins VCMA and VCMB and

ground to ensure a low-noise common-mode output voltage. When AC-coupled, these

pins can be used to set the common-mode reference for the analog inputs, for instance

via a transformer middle point.

11.2.4 Biasing

The common-mode input voltage, VI(cm), at the inputs to the sample-and-hold stage

(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal

performance.

11.3 Clock input

11.3.1 Drive modes

The ADC1613D can be driven differentially (LVPECL). It can also be driven by a

single-ended LVCMOS signal connected to pin CLKP (pin CLKM should be connected to

ground via a capacitor) or pin CLKM (pin CLKP should be connected to ground via a

capacitor).

Fig 15. Reference equivalent schematic

1.5 V

VCMA

VCMB

0.1

μF

PACKAGE

ESD

PARASITICS

005aaa077

COMMON MODE

REFERENCE

ADC CORE

a. Rising edge LVCMOS

b. Falling edge LVCMOS

Fig 16. LVCMOS single-ended clock input

LVCMOS

clock input

CLKP

CLKM

005aaa174

005aaa053

LVCMOS

clock input

CLKP

CLKM

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ADC1613D Datasheet(PDF) 19 Page - NXP Semiconductors

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