APRIL 2004

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 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

NETWORK SEARCH ENGINE

32K x 72 Entries

Datasheet

Brief

75N43102

Device Description

IDT provides proven, industry-leading network search engines

(NSEs) that enable and accelerate the intelligent processing of network

services in communications equipment. As a part of the complete IDT

classificationsubsystemthatincludescontentinspectionengines,theIDT

family of NSEs delivers high-performance, feature-rich, easy-to-use,

integrated search accelerators.

The IDT 75N43102 is ideally suited for cost-sensitive applications

in the enterprise and access markets. It is a full-ternary 32K x 72 entry

device where each entry location in the NSE has both a Data entry and

an associated Mask entry. The NSE devices integrate content addres-

sable memory (CAM) technology with high-performance logic. The

devicecanperformLookupoperationsplusReadandWritemaintenance

operations.

The IDT 75N43102 NSE device has a bi-directional bus that is a

multiplexedaddressanddatabusthatcansupport62.5millionsustained

searches per second. This device can be configured to enable multiple

width lookups from 72 to 288 bits wide. The IDT 75N43102 requires a

The IDT 75N43102 NSE utilizes the latest high-performance 1.5V

CMOS processing technology and is packaged in a JEDEC Standard,

256 pin low profile Ball Grid Array.

To request the full IDT75N43102 datasheet, please contact your local

IDT Sales Representative or call 1-800-345-7015

5346 drw02

Figure 1.0 ASIC / FPGA Compatible NSE

IDT 75N43102

Network

Search

Engine

Configuration Registers

CLK2X

÷

CCLK

÷2

CONFIGIN

MATCHIN

P

R

I

O

R

I

T

Y

E

N

C

O

D

E

R

S

I

Z

E

L

O

G

I

C

DATA

D

E

C

O

D

E

Address

I N S T RUCT I O N

MATCHOUT

REQDATA

REQSTB

R/W

6435 drw 01

RST

Command Bus

PHASEN

Global Mask Registers

Request

Bus

Index

Bus

CONFIGOUT

32KX72

Block Diagram

System Configurations

The IDT NSEs are designed to fulfill the needs of various types of

networking systems. In solutions requiring data searching such as

routers, a system configuration as shown in Figure 1.0 may be realized.

In this compatible configuration, the NSE interfaces directly to an

ASIC/ FPGA for lookups and routes an Index directly back to the ASIC/

FPGA. Control of the associated handshake signals is provided by the

NSEs for this configuration.

ASIC

or

FPGA