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LH543601 Datasheet(PDF) 2 Page - Sharp Corporation |
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LH543601 Datasheet(HTML) 2 Page - Sharp Corporation |
2 / 43 page ![]() FUNCTIONAL DESCRIPTION (cont’d) Two mailbox registers provide a separate path for passing control words or status words between ports. Each mailbox has a New-Mail-Alert Flag, which is syn- chronized to the reading port’s clock. This mailbox func- tion facilitates the synchronization of data transfers between asynchronous systems. Data-bypass mode allows Port A to directly transfer data to or from Port B at reset. In this mode, the device acts as a registered transceiver under the control of Port A. For instance, a master processor on Port A can use the data bypass feature to send or receive initializa- tion or configuration information directly, to or from a peripheral device on Port B, during system startup. A word-width-select option is provided on Port B for 36-bit, 18-bit, or 9-bit data access. This feature allows word-width matching between Port A and Port B, with no additional logic needed. It also ensures maximum utiliza- tion of bus bandwidths. A Byte Parity Check Flag at each port monitors data integrity. Control-Register bit 0 (zero) selects the parity mode, odd or even. This bit is initialized for odd data parity at reset; but it may be reprogrammed for even parity, or back again to odd parity, as desired. 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 VCCO D10A D9A D8A VSSO D7A D6A D5A D4A D3A D2A D1A D0A RS RT1 D1B D2B D3B D4B D5B D6B D7B D8B D9B D10B D11B VCCO VSSO VSSO VCCO VSSO VCCO 49 50 D0B VCCO D24A D25A D26A VSSO D27A D28A D29A D30A D31A D32A D33A D34A D35A RT2 D35B D34B D33B D32B D31B D30B D29B D28B D27B D26B D25B VCCO VSSO VSS VSSO VCCO VSSO VCCO 543601-30 TOP VIEW CHAMFERED EDGE Figure 1. Pin Connections for 132-Pin PQFP Package (Top View) PIN CONNECTIONS LH543601 256 × 36 × 2 Bidirectional FIFO 2 |
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