LH543601 datasheet(17/43 Pages) SHARP

Part #	LH543601

Description	256 x 36 x 2 Bidirectional FIFO

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Manufacturer	SHARP [Sharp Corporation]

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TIMING DIAGRAMS

RS

A

CK

EN

HF, AF, FF, MBF

A

EF, AE

EH

t

ES

t

EH

t

ES

t

RS

t

EH

t

ES

t

EH

t

ES

t

CK

B

EN

B

RSS

t

RSH

t

RSS

t

RSS

t

RSH

t

RSS

t

RF

t

RF

t

NOTES:

1. RS overrides all other input signals, except for R/WA, ENA, and REQA. It operates

asynchronously. RS operates whether or not ENA and/or ENB are asserted. However,

at least one rising edge and one falling edge of both CKA and CKB must occur while

RS is being asserted (is LOW), with timing as defined by tRSS and tRSH.

2. Otherwise, tRSS, tRSH need not be met unless the rising edge of CKA and/or CKB

occurs while that clock is enabled.

3. The parity-check even/odd selection (Control Register bit 00) is initialized to odd byte

parity at reset (HIGH).

4. The AE and AF flag offsets are initialized to eight locations from the boundary at reset.

543601-26

REQ

A

tRQS

tRQH

REQ

B

tRQS

tRQH

tRQS

tRQH

tRQS

tRQH

Figure 8.

Reset Timing

256

× 36 × 2 Bidirectional FIFO

LH543601

17

Similar Part No. - LH543601

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	LH543621	475Kb / 57P	512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO

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Sharp Corporation	LH5420	2Mb / 35P	256 x 36 x 2 Bidirectional FIFO
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Integrated Device Techn...	IDT72V3624	362Kb / 34P	3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
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LH543601 Datasheet(PDF) 17 Page - Sharp Corporation

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