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LH543601 Datasheet(PDF) 10 Page - Sharp Corporation |
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LH543601 Datasheet(HTML) 10 Page - Sharp Corporation |
10 / 43 page ![]() OPERATIONAL DESCRIPTION Reset The device is reset whenever the asynchronous Reset (RS) input is taken LOW, and at least one rising edge and one falling edge of both CKA and CKB occur while RS is LOW. A reset operation is required after power-up, before the first write operation may occur. The LH543601 is fully ready for operation after being reset. No device program- ming is required if the default states described below are acceptable. A reset operation initializes the read-address and write-address pointers for FIFO #1 and FIFO #2 to those FIFO’s first physical memory locations. If the respective outputs are enabled, the initial contents of these first locations appear at the outputs. FIFO and mailbox status flags are updated to indicate an empty condition. In addition, the programmable-status-flag offset values are initialized to eight. Thus, the AE1/AE2 flags get asserted within eight locations of an empty condition, and the AF1/AF2 flags likewise get asserted within eight locations of a full condition, for FIFO #1/FIFO #2 respectively. Bypass Operation During reset (whenever RS is LOW) the device acts as a registered transceiver, bypassing the internal FIFO memories. Port A acts as the master port. A write or read operation on Port A during reset transfers data directly to or from Port B. Port B is considered to be the slave, and cannot perform write or read operations independently on its own during reset. The direction of the bypass data transmission is deter- mined by th R/WA control input, which does not get overridden by the RS input. Here, a ‘write’ operation means passing data from Port A to Port B, and a ‘read’ operation means passing data from Port B to Port A. The bypass capability may be used to pass initializa- tion or configuration data directly between a master proc- essor and a peripheral device during reset. Address Modes Address pins select the device resource to be accessed by each port. Port A has three resource-regis- ter-select inputs, A0A, A1A, and A2A, which select between FIFO access, mailbox-register access, control-register access (write only), and programmable flag-offset-value- register access. Port B has a single address input, A0B, to select between FIFO access or mailbox-register ac- cess. The status of the resource-register-select inputs is sampled at the rising edge of an enabled clock (CKA or CKB). Resource-register select-input address definitions are summarized in Table 1. FIFO Write Port A writes to FIFO #1, and Port B writes to FIFO #2. A write operation is initiated on the rising edge of a clock (CKA or CKB) whenever: the appropriate enable (ENA or ENB) is held HIGH; the appropriate request (REQA or REQB) is held HIGH; the appropriate Read/Write control (R/WA or R/WB) is held LOW; the FIFO address is selected for the address inputs (A2A – A0A or A0B); and the prescribed setup times and hold times are observed for all of these signals. Setup times and hold times must also be observed on the data-bus pins (D0A – D35A or D0B – D35B). Normally, the appropriate Output Enable signal (OEA or OEB) is HIGH, to disable the outputs at that port, so that the data word present on the bus from external sources gets stored. However, a ‘loopback’ mode of operation also is possible, in which the data word supplied by the outputs of one internal FIFO is ‘turned around’ at the port and read back into the other FIFO. In this mode, the outputs at the port are not disabled. To remain within specification for all timing parameters, the Clock Cycle Frequency must be reduced slightly below the value which otherwise would be permissible for that speed grade of LH543601. When a FIFO full condition is reached, write operations are locked out. Following the first read operation from a full FIFO, another memory location is freed up, and the corresponding Full Flag is deasserted (FF = HIGH). The first write operation should begin no earlier than a First Write Latency (tFWL) after the first read operation from a full FIFO, to ensure that correct read data are retrieved. FIFO Read Port Areads from FIFO #2, and Port B reads from FIFO #1. A read operation is initiated on the rising edge of a clock (CKA or CKB) whenever: the appropriate enable (ENA or ENB) is held HIGH; the appropriate request (REQA or REQB) is held HIGH; the appropri ate Read/Write control (R/WA or R/WB) is held HIGH; the FIFO address is selected for the address inputs (A2A – A0A or A0B); and the prescribed setup times and hold times are observed for all of these signals. Read data Table 1. Resource-Register Addresses A2A A1A A0A RESOURCE PORT A HHH FIFO HH L Mailbox HL H AF2, AE2, AF1, AE1 Flag Offsets Register (36-Bit Mode) HL L Control Register (Parity Mode) LH H AE1 Flag Offset Register LH L AF1 Flag Offset Register LL H AE2 Flag Offset Register LL L AF2 Flag Offset Register A0B RESOURCE PORT B H FIFO L Mailbox LH543601 256 × 36 × 2 Bidirectional FIFO 10 |
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