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LH543601 Datasheet(PDF) 9 Page - Sharp Corporation |
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LH543601 Datasheet(HTML) 9 Page - Sharp Corporation |
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9 / 43 page  AC ELECTRICAL CHARACTERISTICS 1 (VCC = 5 V ± 10%, TA = 0°C to 70°C) SYMBOL DECRIPTION –20 –25 –30 –35 UNITS MIN MAX MIN MAX MIN MAX MIN MAX fCC Clock Cycle Frequency — 50 — 40 — 33 — 28.5 MHz tCC Clock Cycle Time 20 — 25 — 30 — 35 — ns tCH Clock HIGH Time 8 — 10 — 12 — 15 — ns tCL Clock LOW Time 8 — 10 — 12 — 15 — ns tDS Data Setup Time 10 — 12 — 13 — 15 — ns tDH Data Hold Time 0—0—0—0 — ns tES Enable Setup Time 10.4 — 13 — 15 — 15 — ns tEH Enable Hold Time 0—0—0—0 — ns tRWS Read/Write Setup Time 10.4 — 13 — 15 — 18 — ns tRWH Read/Write Hold Time 0—0—0—0 — ns tRQS Request Setup Time 12 — 15 — 18 — 21 — ns tRQH Request Hold Time 0—0—0—0 — ns tAS Address Setup Time 6 12 —15—18—21 — ns tAH Address Hold Time 6 0—0—0—0 — ns tA Data Output Access Time — 12.8 — 16 — 20 — 25 ns tACK Acknowledge Access Time — 12 — 15 — 20 — 25 ns tOH Output Hold Time 2.0 — 2.0 — 2.0 — 2.0 — ns tZX Output Enable Time, OE LOW to D0 – D35 Low-Z 2 1.5 — 2.0 — 3.0 — 3.0 — ns tXZ Output Disable Time, OE HIGH to D0 – D35 High-Z 2 — 9 — 12—15— 20 ns tEF Clock to EF Flag Valid (Empty Flag) — 17.6 — 22 — 25 — 30 ns tFF Clock to FF Flag Valid (Full Flag) — 17.6 — 22 — 25 — 30 ns tHF Clock to HF Flag Valid (Half-Full) — 17.6 — 22 — 25 — 30 ns tAE Clock to AE Flag Valid (Almost- Empty) —16—20—25— 30 ns tAF Clock to AF Flag Valid (Almost-Full) — 16 — 20 — 25 — 30 ns tMBF Clock to MBF Flag Valid (Mailbox Flag) —12—15—20— 25 ns tPF Data to Parity Flag Valid — 13.6 — 17 — 20 — 25 ns tRS Reset/Retransmit Pulse Width 7 32/20 — 40/25 — 52/30 — 65/35 — ns tRSS Reset/Retransmit Setup Time 3 16 —20—25—30 — ns tRSH Reset/Retransmit Hold Time 3 8 — 10—15—20 — ns tRF Reset LOW to Flag Valid — 28 — 35 — 40 — 45 ns tFRL First Read Latency 4 20 —25—30—35 — ns tFWL First Write Latency 5 20 —25—30—35 — ns tBS Bypass Data Setup 12 — 15 — 18 — 21 — ns tBH Bypass Data Hold 3—5—5—5 — ns tBA Bypass Data Access — 18 — 20 — 25 — 30 ns NOTES: 1. Timing measurements performed at ‘AC Test Condition’ levels. 2. Values are guaranteed by design; not currently production tested. 3. tRSS and/or tRSH need not be met unless a rising edge of CKA occurs while ENA is being asserted, or else a rising edge of CKB occurs while ENB is being asserted. 4. tFRL is the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data. 5. tFWL is the minimum first-read-to-first-write delay, following a full condtion, which is required to assure successful writing of data. 256 × 36 × 2 Bidirectional FIFO LH543601 9 |
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