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LH540215 Datasheet(PDF) 6 Page - Sharp Corporation |
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LH540215 Datasheet(HTML) 6 Page - Sharp Corporation |
6 / 48 page PIN DESCRIPTIONS PIN NAME PIN TYPE 1 DESCRIPTION D0 – D17 Data Inputs I Data inputs from an 18-bit bus. RS Reset I When RS is taken LOW, the FIFO’s internal read and write pointers are set to address the first physical location of the RAM array; FF, PAF, and HF go HIGH; and PAE and EF go LOW. The programmable-flag-offset registers and the Control Register are set to their default values. (But see the description of EMODE, below.) A reset operation is required before an initial read or write operation after power-up. EMODE Enhanced Operating Mode I When EMODE is tied LOW, the default setting for Control Register bits 00-05 after a reset operation changes to HIGH rather than LOW, thus enabling all Control-Register-controllable Enhanced Operating Mode features, and allowing access to the Control Register for reprogramming or readback. (See Tables 1, 2, and 5.) If this behavior is desired, EMODE may be grounded; however, Control Register bits 00-05 still may be individually programmed to selectively enable or disable certain of the Enhanced Mode features, even though those features associated with interlocked-paralleled operation always are enabled whenever EMODE is being asserted. (See Table 2.) Alternatively, EMODE may be tied to VCC, so that the FIFO is functionally IDT-compatible, and the Control Register is not accessible or visible, and all of its bits remain LOW. Controlling EMODE dynamically during system operation is not recommended. WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK, whenever WEN (Write Enable) is being asserted (LOW), and LD is HIGH. If LD is LOW, a programmable register rather than the internal FIFO memory is written into. In the Enhanced Operating Mode, WEN2 is ANDed with WEN to produce an effective internal write-enable signal. 2 WEN Write Enable I When WEN is LOW and LD is HIGH, an 18-bit data word is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is HIGH, the FIFO internal memory continues to hold the previous data. (See Table 3.) Data will not be written into the FIFO if FF is LOW. In the Enhanced Operating Mode, WEN2 is ANDed with WEN to produce an effective internal write-enable signal. 2 RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK whenever REN (Read Enable) is being asserted (LOW), and LD is HIGH. If LD is LOW, a programmable register rather than the internal FIFO memory is read from. In the Enhanced Operating Mode, REN2 is ANDed with REN (and whenever Control Register bit 05 is HIGH, also with OE) to produce an effective internal read-enable signal. 2 REN Read Enable I When REN is LOW and LD is HIGH, an 18-bit data word is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH, and/or also when EF is LOW, the FIFO’s output register continues to hold the previous data word, whether or not Q0 – Q17 (the data outputs) are enabled. (See Table 3.) In the Enhanced Operating Mode, REN2 is ANDed with REN (and whenever Control Register bit 05 is HIGH, also with OE) to produce an effective internal read-enable signal. 2 OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO’s outputs are in high-Z (high-impedance) state. In the Enhanced Operating Mode, OE not only continues to control the outputs in this same manner, but also can function as an additional ANDing input to the combined effective read-enable signal, along with REN and REN2, whenever Control Register bit 05 is HIGH. (See Table 5.) 2 1 I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level 2 The ostensible differences in signal assertiveness are reconciled before ANDing. BOLD ITALIC = Enhanced Operating Mode LH540215/25 512 x 18/1024 x 18 Synchronous FIFO 6 |
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