LH540215 datasheet(42/48 Pages) SHARP

Part #	LH540215

Description	512 x 18 / 1024 x 18 Synchronous FIFO

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Manufacturer	SHARP [Sharp Corporation]

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Depth Cascading Using Pipelining

Using the pipelining approach, depth cascading is

implemented by connecting the required number of

LH540215/25s in series. Within the cascade, the Data

Outputs of each device are connected to the Data Inputs

of the next device. (See Figure 29a.) All devices in the

cascade must be in

the Enhanced Operating Mode;

thus, their

EMODE inputs must be grounded.

Successive devices in the cascade are crosscoupled;

they control each other, using a ‘handclasp’ scheme for

crossconnecting their control inputs and their status out-

puts. (See again Figure 29a.) The input side of the first

device, and the output side of the last device, are not

crosscoupled to other devices. Their control/status and

clock pins are connected to the external system.

For the FIFO devices within the cascade, transferring

data from each device to the next device is governed by

a clock. Preferably, the same clock should be used at

every FIFO-to-FIFO data-transfer interface boundary

within the cascade. This ‘Transfer Clock’ may be either

the external Write Clock, or the external Read Clock. If

both of these two clocks are periodic and free-running,

the faster of the two is the obvious choice for the ‘Transfer

Clock.’ Of course, in principle, the ‘Transfer Clock’ may

even be some other, totally-different clock.

The Empty Flag of each device is used to govern

writing into the next device, and the Full Flag of each

device is used to govern reading from the preceding

device. Since the standard Empty Flag EF occurs one

RCLK cycle too early to properly enable/disable the next

device,

the duplicate Empty Flag EF2 is used instead;

EF2 is an exact copy of EF, except that it is delayed

by one full RCLK cycle with respect to EF.

Also, since the usual enable signals WEN and REN

have the wrong polarity to function properly in this ‘hand-

clasp’ mode, they are grounded for all devices within the

cascade.

The duplicate but inverted signals WEN2

and REN2 are used instead.

EF2, WEN2, and REN2 are available only in En-

hanced Operating Mode. They share the same pins

which in IDT-Compatible Operating Mode are used

respectively for RXO, WXI, and RXI. Hence, for pipe-

lined operation, all devices in the cascade must be in

the Enhanced Operating Mode; their EMODE control

inputs must be grounded.

When all of the foregoing conditions have been met in

the interconnection of the pipelined array, then: At each

device-to-device interface boundary within the array, a

data word is transferred from the upstream device to the

downstream device after

every transfer-clock rising edge,

as long as the upstream device is not empty and the

downstream device is not full.

There is one possible anomalous behavior, which can

occur if at any time the device upstream from a FIFO-to-

FIFO boundary (‘device n-1’) becomes totally empty, at

the same time as the downstream device (‘device n’)

becomes totally full. Under these relatively-infrequent

conditions, one extra copy of the last word transferred out

of device n-1, which remains still available at the outputs

of that device, gets introduced into the data stream. The

simple circuit illustrated in Figure 29b avoids introducing

this extra word, and does not slow down the operation of

the pipeline if it is implemented with logic which is suffi-

ciently fast. Table 6 indicates the speed requirements for

this circuit which correspond to the various speed grades

of LH540215/25. If the infrequent introduction of such an

extra word is not of concern for a given cascaded-

LH540215/25 application, the circuit of Figure 29b may

safely be omitted.

Table 6. Required External-Logic Speeds for

Pipelined Depth-Cascading Operation at

Maximum Rate of Speed Grade

SPEED GRADE (CYCLE TIME)

20 ns

25 ns

35 ns

Ta

≤ 8 ns

≤ 10 ns

≤ 15 ns

Tb

≤ 15 ns

≤ 19 ns

≤ 28 ns

NOTES:

1.

Ta is the setup time for the signal ‘FF (DEVICE n),’ including the

delay of the assertive-LOW AND gate, with respect to the clock.

2.

Tb is the clock-to-output time for the signal ‘WEN2 (DEVICE n),’

including the delay of the assertive-HIGH AND gate.

Two PLDs (Programmable Logic Devices) suffice to

implement the circuit of Figure 29b ten times, which

allows for the cascading of LH540215/25s eleven deep.

The choice of a GAL20RA10B-10 PLD to implement the

flipflop and the two AND gates at its inputs, and a

GAL22V10C-5 PLD to implement the simple AND gate

which follows the flipflop, provides a sufficiently fast circuit

to allow a cascade of LH540215/25-20 devices (the fast-

est speed grade presently offered by Sharp) to operate

with no speed degradation. Designers experienced in

using PLDs may recognize other implementations.

BOLD ITALIC = Enhanced Operating Mode

LH540215/25

512 x 18/1024 x 18 Synchronous FIFO

42

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