LH540215 datasheet(39/48 Pages) SHARP

Part #	LH540215

Description	512 x 18 / 1024 x 18 Synchronous FIFO

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Manufacturer	SHARP [Sharp Corporation]

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39 / 48 page

When standalone-mode LH540215/25 devices are

paralleled, the behavior of the status flags is identical for

all devices; so, in principle, a representative value for

each of these flags could be derived from any one device.

In practice, it is better to derive ‘composite’ flag values

using external logic, since there may be minor speed

variations between different actual devices. After writing

or reading have been in a disabled state, the process of

re-enabling should be gated by the slowest FIFO.

For m paralleled FIFOs, the form of this external

composite-flag logic may be an OR gate with m asser-

tive-LOW inputs and an assertive-LOW output. In keep-

ing with deMorgan’s Theorem, such a gate may be

implemented as an AND gate with m assertive-HIGH

inputs and an assertive-HIGH output. Figure 27 illustrates

the case m = 2.

The LH540215/25 architecture supports two very dif-

ferent methods of depth cascading:

Token passing, which follows the scheme used in the

pin-compatible and functionally-compatible Integrated

Device Technology IDT72205B /15B/25B/35B/45B

FIFOs, which the LH540215/25 can directly replace.

Pipelining, which follows the scheme used in the Texas

Instruments SN74ACT7801/11/81 FIFOs, and also in the

Sharp LH543620 1024

×36 FIFO. The SN74ACT7801/11/81

pinout closely resembles the LH540215/25 pinout, but is

not identical.

Depth Cascading Using Token Passing

Using the token-passing approach, depth cascading

is implemented by configuring the required number of

LH540215/25s in a circular ‘ring’ fashion, with the Expan-

sion Out outputs (WXO/HF and RXO/

EF2) of each device

tied to the Expansi on In inputs (WXI/

WEN2 and

RXI/

REN2) of the next device. (See Figure 28.) Because

a reset operation forces the WXO/HF and RXO/

EF2

outputs HIGH for each device, the WXI/

WEN2 and

RXI/

REN2 inputs for the next device are HIGH during the

reset operation; thus, these two inputs are HIGH for all

devices in the ring. (See Tables 1 and 2, and also Figure

28.) All devices in the cascade must be in the IDT-Com-

patible Operating Mode; thus, their

EMODE inputs must

be tied to Vcc.

One FIFO in the cascade must be designated as the

‘first-load’ device, by tying its First Load input (FL/

RT) to

ground. All other devices must have their FL/

RT inputs

tied HIGH. Under these circumstances, the Retransmit

function is not available for use.

In this mode, the control inputs which govern writing

(WCLK and WEN) and the control inputs which govern

reading (RCLK and REN) are shared by all devices, while

logic within each LH540215/25 governs the steering of

data. The common Data Inputs of all devices are tied

together; but only one LH540215/25 is enabled during

any given write cycle. Likewise, the common three-state

Data Outputs of all devices are wire-ORed together; but

only one LH540215/25 is enabled, including its three-

state outputs, during any given read cycle. A data word is

handled only by one device as it passes through the

cascade of FIFOs, regardless of how many FIFOs are

being cascaded together.

In the token-passing depth-cascaded mode, external

logic should be used to generate a composite Full Flag

and a composite Empty Flag, by ANDing the FF outputs

of all LH540215/25 devices together and by ANDing the

EF outputs of all devices together, using AND gates with

assertive-LOW inputs and an assertive-LOW output.

Here, the meaning of these composite flags is direct: the

cascade of FIFOs is full, if and only if all k FIFOs belonging

to the cascade are individually full; and similarly for empty.

In keeping with deMorgan’s Theorem, these k-input as-

sertive-LOW AND gates are implemented physically as

k-input assertive-HIGH OR gates. Figure 28 illustrates the

case k = 3.

Similar external logic also may be used to generate a

composite Programmable Almost-Full Flag and a com-

posite Programmable Almost-Empty Flag, by ANDing the

PAF outputs of all LH540215/25 devices together and by

ANDing the PAE outputs of all devices together. Here,

however, some careful analysis is required, to determine

exactly what the resulting composite flags mean. Their

significance may vary widely, depending on the number

of FIFOs in the cascade, and on the ‘offset’ values which

are present in the offset registers for these FIFOs. More

complex logical combinations of PAF outputs with FF

outputs, and of PAE outputs with EF outputs, may be

found useful in particular applications.

In any case, the Half-Full Flag and the Retransmit

function are not available for devices being used in token-

passing depth-cascaded mode.

BOLD ITALIC = Enhanced Operating Mode

512 x 18/1024 x 18 Synchronous FIFO

LH540215/25

39

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