LH540215 datasheet(36/48 Pages) SHARP

Part #	LH540215

Description	512 x 18 / 1024 x 18 Synchronous FIFO

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Manufacturer	SHARP [Sharp Corporation]

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Q [17:0]

RCLK

FL/RT

FF

PAF

HF

PAE

EF

REN1

540215-28

DR1

tENS

tRSF

DRT1

2

DRT2

NOTES:

1. It is not necessary for REN to be LOW for the device to recognize a retransmit request.

2. In order to actually read data words from the memory arrary, in IDT-Compatible

Operating Mode, REN = LOW;

in Enhanced Operating Mode, also REN2 = HIGH

(and OE = LOW, if Control Register bit 05 = HIGH). In any case, LD = HIGH.

3. DRT1 is the data item in physical location zero of the FIFO memory array.

4. The asynchronous intermediate flags (corresponding to LOW Control-Register bits) will

show correct status three RCLK cycles after a retransmit operation, as is shown above.

(RT3, in the above RCLK waveform.)

5. The intermediate flags which have been synchronized to RCLK, by setting the appropriate

Control-Register bits to HIGH will show correct status after

, four RCLK cycles after a

retransmit operation. (RT4, in the above RCLK waveform.)

6. The intermediate flags which have been synchronized to WCLK, by setting the appropriate

Control-Register bits HIGH, will show correct status on the second WCLK rising edge after

,

assuming that tSKEW1 was satisfied at

; otherwise the flags will become valid on the third

WCLK rising edge after

.

7. Immediately after a reset operation, before any write operations have taken place, a retransmit

operation is a 'no-op', and does not change the state of any FIFO registers or flags.

8. In the special case that the FIFO memory array contains only one valid data item, the status

of HF and PAF should be ignored on a retransmit.

tENS

tENH

DR2

tA

tPAF

R1

R2

RT1

RT2

RT3

RT4

tWFF

tHF

tPAE

tREF

NEW VALID FF

NEW VALID PAF

NEW VALID HF

NEW VALID PAE

NEW VALID EF

UNKNOWN

PREVIOUS VALID FF

PREVIOUS VALID PAF

PREVIOUS VALID HF

PREVIOUS VALID PAE

PREVIOUS VALID EF

AB

A

B

tA

A

Figure 21. Retransmit Timing

TIMING DIAGRAMS (cont’d)

LH540215/25

512 x 18/1024 x 18 Synchronous FIFO

36

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