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LH540215 Datasheet(PDF) 35 Page - Sharp Corporation |
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LH540215 Datasheet(HTML) 35 Page - Sharp Corporation |
35 / 48 page ![]() 540215-26 Q0 - Q17 REN RCLK HF OE WEN D0 - D17 WCLK DATA READ tDS DATA IN OUTPUT REGISTER tDS DATA WRITE 1 DATA WRITE 2 tENS tENH tENH tENS tSKEW2(1) tSKEW2(1) tHFS tHFS tHFS tA NOTE: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for HF to change predictably during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then it is not guaranteed that HF will change state until the next following RCLK edge. 2. The internal state of the FIFO: At , half+1 words. At , exactly half full. At , half+1 words again. LOW Enhanced Operating Mode Timing Diagram A B C A B C tENS tENH Figure 20. Half-Full-Flag Timing, When Synchronized to Output Port (Enhanced Operating Mode) TIMING DIAGRAMS (cont’d) 512 x 18/1024 x 18 Synchronous FIFO LH540215/25 35 |
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