LH540215 datasheet(34/48 Pages) SHARP

Part #	LH540215

Description	512 x 18 / 1024 x 18 Synchronous FIFO

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Manufacturer	SHARP [Sharp Corporation]

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34 / 48 page

540215-25

Q0 - Q17

REN

RCLK

HF

OE

WEN

D0 - D17

WCLK

DATA WRITE

DATA READ

LOW

DATA IN

OUTPUT REGISTER

tSKEW11

tDS

tSKEW11

tHFS

tENS

tENH

tENS

tENH

tA

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a

rising WCLK edge for HF to change predictably during the current

clock cycle. If the time between the rising edge of RCLK and the

rising edge of WCLK is less than tSKEW1, then it is not guaranteed

that HF will change state until the next following WCLK edge.

2. The internal state of the FIFO:

At

, exactly half full.

At

, half+1 words.

At

, exactly half full again.

Enhanced Operating Mode Timing Diagram

NO WRITE

A

B

C

A

B

C

Figure 19. Half-Full-Flag Timing, When Synchronized

to Input Port (Enhanced Operating Mode)

TIMING DIAGRAMS (cont’d)

LH540215/25

512 x 18/1024 x 18 Synchronous FIFO

34

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Manufacturer	Part #	Datasheet	Description
Integrated Device Techn...	IDT72511	434Kb / 28P	PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18
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Texas Instruments	SN74V215	590Kb / 43P	[Old version datasheet] 512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
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	SN74V215	555Kb / 40P	[Old version datasheet] 512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
Sharp Corporation	LH543620	269Kb / 38P	1024 x 36 Synchronous FIFO
Integrated Device Techn...	IDT72V205	214Kb / 25P	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
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LH540215 Datasheet(PDF) 34 Page - Sharp Corporation

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