LH540215 datasheet(30/48 Pages) SHARP

Part #	LH540215

Description	512 x 18 / 1024 x 18 Synchronous FIFO

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Manufacturer	SHARP [Sharp Corporation]

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540215-23

Q0 - Q17

REN

RCLK

PAE

OE

WEN

D0 - D17

WCLK

DATA READ

tDS

DATA IN OUTPUT REGISTER

tDS

DATA WRITE 1

DATA WRITE 2

tENS

tENH

tENS

tSKEW2(1)

tPAES

tA

LOW

NOTES:

1. tSKEW2 is the minimum time between a rising WCLK edge and a

rising RCLK edge for PAE to change predictably during the current

clock cycle. If the time between the rising edge of WCLK and the

rising edge of RCLK is less than tSKEW2, then it is not guaranteed

that PAE will change state until the next following RCLK edge.

2. PAE offset = q. Also, number of data words written into FIFO already = q.

3. The internal state of the FIFO:

At

, q+1 words.

At

, q words.

At

, q+1 words again.

Enhanced Operating Mode Timing Diagram

B

A

C

A

B

C

Figure 15. Programmable-Almost-Empty Flag Timing,

When Synchronous (Enhanced Operating Mode)

TIMING DIAGRAMS (cont’d)

LH540215/25

512 x 18/1024 x 18 Synchronous FIFO

30

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Manufacturer	Part #	Datasheet	Description
Integrated Device Techn...	IDT72511	434Kb / 28P	PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18
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Sharp Corporation	LH543611	475Kb / 57P	512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO
Texas Instruments	SN74V215	590Kb / 43P	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
	SN74V215	600Kb / 43P	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
	SN74V215	555Kb / 40P	512 X 18, 1024 X 18, 2048 X 18, 4096 X 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES
Sharp Corporation	LH543620	269Kb / 38P	1024 x 36 Synchronous FIFO
Integrated Device Techn...	IDT72V205	214Kb / 25P	3.3 VOLT CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18
Cypress Semiconductor	CY7C4205	689Kb / 25P	256/512/1K/4K x 18 Synchronous FIFOs

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LH540215 Datasheet(PDF) 30 Page - Sharp Corporation

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