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LH540215 Datasheet(PDF) 26 Page - Sharp Corporation |
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LH540215 Datasheet(HTML) 26 Page - Sharp Corporation |
26 / 48 page ![]() 540215-9 Q0 - Q17 REN RCLK FF OE WEN D0 - D17 WCLK DATA WRITE DATA WRITE DATA READ LOW DATA IN OUTPUT REGISTER NEXT DATA READ NO WRITE NO WRITE tSKEW11 tDS tDS tSKEW11 tWFF tWFF tWFF tENS tENH tENS tENH tA tA NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change predictably during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then it is not guaranteed that FF will change state until the next following WCLK edge. Figure 10. Full-Flag Timing TIMING DIAGRAMS (cont’d) LH540215/25 512 x 18/1024 x 18 Synchronous FIFO 26 |
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