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LH540215 Datasheet(PDF) 25 Page - Sharp Corporation |
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LH540215 Datasheet(HTML) 25 Page - Sharp Corporation |
25 / 48 page ![]() tDS tENS Q0 - Q17 REN RCLK EF OE WEN 540215-8 D0 (FIRST VALID WRTE) D1 D2 D3 D4 D0 D1 tFRL (2) tSKEW2 (1) tREF tA (3) tA tOLZ tOE D0 - D17 WCLK NOTES: 1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change predictably during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then it is not guaranteed that FF will change state until the next following WCLK edge. 2. tFRL (First-Read Latency) is the minimum time between a rising WCLK edge and a rising RCLK edge to assure a correct readout of the first data word D0 in response to the next RCLK edge. Thus, tFRL = tCLK + tSKEW2. If tFRL is not met, D0 may be available either at tCLK + tSKEW2, or after one more clock cycle delay at 2 tCLK + tSKEW2. The First-Read Latency timing restrictions apply only when the FIFO has been empty (EF = LOW). 3. EF may be used to determine when the first data word D0 may be read. D0 always is available on the next cycle after EF has gone HIGH. Figure 9. Latency for the First Data Word After a Reset Operation, With Simultaneous Read and Write TIMING DIAGRAMS (cont’d) 512 x 18/1024 x 18 Synchronous FIFO LH540215/25 25 |
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