LH540215 datasheet(21/48 Pages) SHARP

Part #	LH540215

Description	512 x 18 / 1024 x 18 Synchronous FIFO

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Manufacturer	SHARP [Sharp Corporation]

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in the FIFO’s physical memory, which is 512 for the

LH540215 or 1024 for the LH540225 respectively.

The default value of q after the completion of a reset

operation is one-eighth of the total number of words in the

FIFO-memory array, minus one; 63 for the LH540215 or

127 for the LH540225 respectively. However, q may be

set to any value which does not exceed this total nominal

number of words for the device, as explained in the

description of Load (LD).

If the FIFO has been reset by asserting RS (LOW), and

no write operations have been performed since the com-

pletion of the reset operation, then PAE is LOW. (See

Table 4.)

If q is still at its default value, PAE is LOW whenever

the FIFO is from one-eighth full to completely empty.

In the IDT-Compatible Operating Mode, PAE changes

from HIGH to LOW only after a LOW-to-HIGH transition

of the Read Clock RCLK, and from LOW to HIGH only

after a LOW-to-HIGH transition of the Write Clock WCLK.

Thus, in this operating mode, PAE behaves as an ‘asyn-

chronous flag.’

In the Enhanced Operating Mode, on the other

hand, PAE gets updated only after a LOW-to-HIGH

transition of the Read Clock RCLK, and thus behaves

as a ‘synchronous flag,’ whenever Control Register

bit 01 is HIGH. (See Table 5.)

EMPTY FLAG (EF)

EF goes LOW whenever the FIFO is completely empty.

That is, whenever the FIFO’s internal read pointer has

completely caught up with its internal write pointer; so

that, if another word were to be read out, it would have to

come from the physical memory location which is now in

position to be written into by the next requested write

operation. Read operations are inhibited whenever EF is

LOW, regardless of the assertion or deassertion of Read

Enable (REN).

If the FIFO has been reset by asserting RS (LOW), and

no write operations have been performed since the

completion of the reset operation, then EF is LOW. (See

Table 4.)

EF gets updated after a LOW-to-HIGH transition of the

Read Clock RCLK.

READ EXPANSION OUT/

EMPTY FLAG 2 (RXO/EF2)

RXO/

EF2 is a dual-purpose signal. In ‘standalone’

operation, it has no function. In IDT-compatible ‘cas-

caded’ operation, it behaves as a Read Expansion Output

(RXO) signal to coordinate writing operations with the

next FIFO in the cascade. Under these same conditions,

also, the dual-purpose RXI/

REN2 and WXI/WEN2 inputs

behave as Read Expansion Input (RXI) and Write Expan-

sion Input (WXI) signals respectively.

When two or more LH540215 or LH540225 FIFOs are

operating in IDT-compatible ‘cascaded’ mode as a deeper

‘effective FIFO,’ the dual-purpose RXI/

REN2 and

WXI/

WEN2 inputs behave as Read Expansion Input

(RXI) and Write Expansion Input (WXI) signals respec-

tively. An IDT-style cascade of these FIFO devices has a

‘daisy-chain’ ring configuration; the Read Expansion Input

(RXI) of each FIFO is connected to RXO (RXO/

EF2,

behaving as RXO) of the previous FIFO in the ring, with

RXI of the ‘first-load’ or ‘master’ FIFO being connected to

RXO of the last FIFO so as to complete the ring. Similar

connections are made for each FIFO in the ring, parallel

to these RXO-to-RXI connections, for Write Expansion

Input (WXI) and Write Expansion Output (WXO).

When the last physical location has been read in a

FIFO operating in IDT-style cascaded mode, a LOW-go-

ing pulse is emitted by that FIFO on its RXO output;

otherwise, RXO remains constantly HIGH. This LOW-go-

ing RXO pulse serves as a ‘read token’ in the token-pass-

ing FIFO-cascading scheme; it is passed on to the next

FIFO in the ring via its RXI input. When this next FIFO

receives the read token, it is activated for reading at the

next valid RCLK.

After a FIFO emits an RXO pulse, the FIFO is deacti-

vated for reading at the next valid RCLK. Also, its data

outputs go into high-Z state, regardless of the assertion

or deassertion of its Output Enable (OE) control input,

until it again receives the token. Simultaneously, the next

FIFO in the ring is activated for reading.

The foregoing description applies both to the ‘first-load’

or ‘master’ FIFO in the ring, and to any and all ‘slave’

FIFOs in the ring. However, RXO has no necessary

function for a FIFO which is operating in ‘standalone’

mode. Consequently, in that mode, RXO is never as-

serted, and remains constantly HIGH. A FIFO is initialized

into ‘standalone’ mode, into ‘cascaded master’ mode, or

into ‘cascaded slave’ mode according to the state of its

WXI/

WEN2, RXI/REN2, and FL/RT control inputs during

a reset operation.

It also may be forced into inter-

locked-paralleled mode by EMODE. (See Table 1,

Table 2, and Table 5.)

In the Enhanced Operating Mode, RXO/EF2 be-

haves as a second Empty Flag EF2. EF2 is an exact

duplicate of the main Empty Flag EF, except that it is

delayed with respect to EF by one full cycle of the

Read Clock RCLK.

DESCRIPTION OF SIGNALS AND

OPERATING SEQUENCES (cont’d)

BOLD ITALIC = Enhanced Operating Mode

512 x 18/1024 x 18 Synchronous FIFO

LH540215/25

21

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