LH540215 datasheet(20/48 Pages) SHARP

Part #	LH540215

Description	512 x 18 / 1024 x 18 Synchronous FIFO

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If the FIFO has been reset by asserting RS (LOW), and

no read operations have been performed since the

completion of the reset operation, PAF goes LOW after

(512-p) write operations for the LH540215, or after

(1024-p) write operations for the LH540225. (See

Table 4.)

If p is still at its default value, PAF is LOW whenever

the FIFO is from seven-eighths full to completely full.

In the IDT-Compatible Operating Mode, PAF changes

from HIGH to LOW only after a LOW-to-HIGH transition

of the Write Clock WCLK, and from LOW to HIGH only

after a LOW-to-HIGH transition of the Read Clock RCLK.

Thus, in this operating mode, PAF behaves as an ‘asyn-

chronous flag.’

In the Enhanced Operating Mode, on the other

hand, PAF gets updated only after a LOW-to-HIGH

transition of the Write Clock WCLK, and thus behaves

as a ‘synchronous flag,’ whenever Control Register

bit 04 is HIGH. (See Table 5.)

WRITE EXPANSION OUT/HALF-FULL FLAG

(WXO/HF)

WXO/HF is a dual-purpose signal. In ‘standalone’ op-

eration, it behaves as a Half-Full Flag (HF), in accordance

with Table 4. In IDT-compatible ‘cascaded’ operation, it

behaves as a Write Expansion Output (WXO) signal to

coordinate writing operations with the next FIFO in the

cascade. Under these same conditions, also, the dual-

purpose WXI/

WEN2 and RXI/REN2 inputs behave as

Write Expansion Input (WXI) and Read Expansion Input

(RXI) signals respectively.

When two or more LH540215 or LH540225 FIFOs are

‘cascaded’ to operate as a deeper ‘effective FIFO,’ in an

IDT-style ‘daisy-chain’ ring configuration, the Write Ex-

pansion Input (WXI) of each FIFO is connected to WXO

of the previous FIFO in the ring, with WXI of the ‘first-load’

or ‘master’ FIFO being connected to WXO of the last FIFO

so as to complete the ring. Similar connections are made

for each FIFO in the ring, parallel to these WXO-to-WXI

connections, for Read Expansion Input (RXI) and Read

Expansion Output (RXO/

EF2, when it is behaving as

RXO).

When the last physical location has been written in a

FIFO operating in cascaded mode, a LOW-going pulse is

emitted by that FIFO on its WXO output, and the FIFO is

deactivated for writing at the next valid WCLK; and the

next FIFO in the ring is simultaneously activated for

writing. Otherwise, WXO remains constantly HIGH when-

ever the FIFO is operating in cascaded mode. This LOW-

going WXO pulse serves as a ‘write token’ in the

‘token-passing’ FIFO-cascading scheme; it is passed on

to the next FIFO in the ring via its WXI input. When this

next FIFO receives the write token, it is activated for

writing at the next valid WCLK.

The foregoing description applies both to the ‘first-load’

or ‘master’ FIFO in the ring, and to any and all ‘slave’

FIFOs in the ring. However, WXO has no necessary

function for FIFOs operating in the ‘standalone’ mode.

Consequently, in that mode, the same output pin is used

for HF; it follows that HF is not available as an output from

any FIFO which is operating in the IDT-compatible cas-

caded mode. A FIFO is initialized into ‘cascaded master’

mode, into ‘cascaded slave’ mode,

into interlocked-par-

alleled mode, or into standalone mode according to the

state of its WXI/

WEN2, RXI/REN2, and FL/RT control

inputs during a reset operation,

and of EMODE. (See

Table 1, Table, 2, and Table 5.)

In standalone

or interlocked-paralleled operation,

HF goes LOW whenever the FIFO is more than half full;

that is, whenever subtracting the value of the FIFO’s

internal read pointer from the value of its internal write

pointer yields a difference which is less than half of the

total nominal number of 18-bit words in the FIFO’s physi-

cal memory, which is 256 for the LH540215 or 512 for the

LH540225 respectively. (See Table 4.) The subtraction is

performed using modular arithmetic, modulo this total

nominal number of words, which is 512 for the LH540215

or 1024 for the LH540225 respectively.

If the FIFO has been reset by asserting RS (LOW), and

it is operating in standalone mode

or in interlocked-par-

alleled mode, and no read operations have been per-

formed since the completion of the reset operation, HF

goes LOW after 257 write operations for the LH540215,

or after 513 write operations for the LH540225. (See

again Table 4.)

In the IDT-Compatible Operating Mode, HF changes

from HIGH to LOW only after a LOW-to-HIGH transition

of the Write Clock WCLK, and from LOW to HIGH only

after a LOW-to-HIGH transition of the Read Clock RCLK.

Thus, in this operating mode, HF behaves as an ‘asyn-

chronous flag.’

In the Enhanced Operating Mode, on the other

hand, HF gets updated only after a LOW-to-HIGH

transition of the Read Clock RCLK, or else after a

LOW-to-HIGH transition of the Write Clock WCLK,

according to the setting of bits 03 and 02 of the

Control Register (see Table 5). Thus, in this mode HF

behaves as a ‘synchronous flag,’ and may be syn-

chronized either to the input side of the FIFO (i.e., to

WCLK), or to the output side of the FIFO (i.e., to

RCLK).

PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)

PAE goes LOW whenever the FIFO is ‘almost empty’;

that is, whenever subtracting the value of the FIFO’s

internal write pointer from the value of its internal read

pointer yields a difference which is less than q + 1, where

‘q’ is the value of the Programmable-Almost-Empty-Flag

Offset. The subtraction is performed using modular arith-

metic, modulo the total nominal number of 18-bit words

BOLD ITALIC = Enhanced Operating Mode

LH540215/25

512 x 18/1024 x 18 Synchronous FIFO

20

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