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LH540215 Datasheet(PDF) 2 Page - Sharp Corporation |
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LH540215 Datasheet(HTML) 2 Page - Sharp Corporation |
2 / 48 page FUNCTIONAL DESCRIPTION NOTE: Throughout this data sheet, a BOLD ITALIC type font is used for all references to Enhanced Operating Mode features which do not function in IDT-Compatible Operating Mode; and also for all references to the re- transmit facility (which is not an IDT72215B/25B FIFO feature), even though it may be used – subject to some restrictions – in either of these two operating modes. Thus, readers interested only in using the LH540215/25 FIFOs in IDT-Compatible Operating Mode may skip over BOLD ITALIC sections, if they wish. The LH540215/25 parts are FIFO (First-In, First-Out) memory devices, based on fully-static CMOS dual-port SRAM technology, capable of containing up to 512 or 1024 18-bit words respectively. They can replace two or more byte-wide FIFOs in many applications, for microprocessor- to-microprocessor or microprocessor-to-bus communica- tion. Their architecture supports synchronous operation, tied to two independent free-running clocks at the input and output ports respectively. However, these ‘clocks’ also may be aperiodic, asynchronous ‘demand’ signals. Almost all control-input signals and status-output signals are synchro- nized to these clocks, to simplify system design. The input and output ports operate altogether inde- pendently of each other, unless the FIFO becomes either totally full or else totally empty. Data flow is initiated at a port by the rising edge of its corresponding clock, and is gated by the appropriate edge-sampled enable signals. The following FIFO status flags monitor the extent to which the internal memory has been filled: Full, Almost- Full, Half-Full, Almost-Empty, and Empty. The Almost-Full and Almost-Empty flag offsets are programmable over the entire FIFO depth; but, during a reset operation, each of these is initialized to a default offset value of 6310 (LH540215) or 12710 (LH540225) FIFO-memory words, from the respective FIFO boundary. If this default offset value is satisfactory, no further programming is required. After a reset operation during which the EMODE control input was not asserted (was HIGH), these FIFOs operate in the IDT-Compatible Operating Mode. In this mode, each part is pin-compatible and functionally-compatible with the IDT72215B/25B part of similar depth and speed grade; and the Control Register is not even accessible or visible to the external-system logic which is controlling the FIFO, although it still performs the same control functions. However, assertion of the EMODE control input during a reset operation leaves Control Register bits 00-05 set, and causes the FIFO to operate in the Enhanced Operating Mode. In essence, asserting EMODE chooses a different default state for the Con- trol Register. The system optionally then may pro- gram the Control Register in any desired manner to activate or deactivate any or all of the Enhanced-Op- erating-Mode features which it can control, including selectable-clock-edge flag synchronization, and read inhibition when the data outputs are disabled. Whenever EMODE is being asserted, interlocked- operation paralleling also is available, by appropriate interconnection of the FIFO’s expansion inputs. The retransmit facility is available during standalone operation, in either IDT-Compatible Operating Mode or Enhanced Operating Mode. (See Tables 1 and 2.) It is inoperative if the FL/ RT input signal is grounded. It is not an IDT72215B/25B feature. The Retransmit control signal causes the internal FIFO read-address pointer to be set back to zero, without affecting the internal FIFO write-address pointer. Thus, the Retransmit control signal also provides a mechanism whereby a block of data delimited by the zero physical address and the current write-address-pointer address may be read out repeatedly, an arbitrary number of times. The only restrictions are that neither the read-ad- dress pointer nor the write-address pointer may ‘wrap around’ during this entire process, and that the retransmit facility is not available during depth-cas- caded operation, either in IDT-Compatible Operating Mode or in Enhanced Operating Mode. (See Tables 1 and 2.) Also, the flags behave differently for a short time after a retransmit operation. Otherwise, the re- transmit facility is available during standalone opera- tion, in either IDT-Compatible Operating Mode or Enhanced Operating Mode. Note that, when FL/RT is being used as RT, RT is an assertive-HIGH signal, rather than assertive-LOW as it is in most other FIFOs having a retransmit facility. Programming the programmable-flag offsets, the tim- ing synchronization of the various status flags, the optional read-suppression functionality of OE, and the behavior of the pointers which access the offset- value registers and the Control Register may be indi- vidually controlled by asserting the signal LD, without any reset operation. When LD is being asserted, and writing is being enabled by asserting WEN, some portion of the input bus word D0 – D17 is used at the next rising edge of WCLK to program one or more of the programmable registers on successive write clocks. Likewise, the values programmed into these programmable registers may be read out for verification by asserting LD and REN, with the outputs Q0 – Q17 enabled. Reading out these pro- grammable registers should not be initiated while they are being written into. Table 3 defines the possible modes of operation for loading and reading out the contents of programmable registers. BOLD ITALIC = Enhanced Operating Mode LH540215/25 512 x 18/1024 x 18 Synchronous FIFO 2 |
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