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LH540215 Datasheet(PDF) 18 Page - Sharp Corporation |
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LH540215 Datasheet(HTML) 18 Page - Sharp Corporation |
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18 / 48 page  But, if EMODE is asserted (LOW), then still another 18-bit data word from the data inputs D0 – D17 is written into the Control Register at the third rising edge of WCLK. At the fourth rising edge of WCLK, writing again occurs to the Programmable-Almost- Empty-Flag-Offset-Value Register; and the same three-step writing sequence gets repeated on sub- sequent WCLK rising edges. The lower nine bits of these offset-value words are made use of by the 512-word LH540215, and the lower ten bits by the 1024-word LH540225. Six active bits are used for the Control Register, by both the LH540215 and the LH540225. There is no restriction on the values which may occur in these offset-value and Control-Reg- ister fields. However, reserved bit positions must be encoded LOW, in order to maintain forward compatibility. Writing contents to these two or three programmable registers does not have to occur all at one time, or to be effected by one single sequence of steps. Whenever LD is being asserted (is LOW) but WEN is not being asserted (is HIGH), the FIFO’s internal programmable-register- write-address pointer maintains its present value, without any writing actually taking place at each rising edge of WCLK. (See Table 3.) Thus, for instance, one or two programmable registers may be written, after which the FIFO may be returned to normal FIFO-array-read/write operation by deasserting LD (to HIGH). Likewise, whenever LD and REN are simultaneously being asserted (are both LOW) the 18-bit data word (zero-filled as necessary) from the Programmable-Al- most-Empty-Flag-Offset-Value Register is read to the data outputs Q0 – Q17 at the first rising edge (LOW-to- HIGH transition) of the read clock (RCLK). (See Table 3.) If LD and REN continue to be simultaneously asserted, another 18-bit data word from the Programmable-Almost- Full-Flag-Offset-Value Register is read to the data outputs Q0 – Q17 at the second rising edge of RCLK. What happens next is determined by the state of the EMODE control input. If it is deasserted (HIGH), the next 18-bit word again comes from the Programmable-Almost- Empty-Flag-Offset-Value Register; it is read to the data outputs Q0 – Q17. But, if EMODE is asserted (LOW), then the next 18-bit data word instead comes from the Control Register; it is read to the data outputs Q0 – Q17 at the third rising edge of RCLK. At the fourth rising edge of RCLK, reading again occurs from the Programma- ble-Almost-Empty-Flag-Offset-Value Register; and the same three-step reading sequence gets repeated on subsequent RCLK rising edges. Reading contents from these two or three programma- ble registers does not have to occur all at one time, or to be effected by one single sequence of steps. Whenever LD is being asserted (is LOW) but REN is not being asserted (is HIGH), the FIFO’s internal programmable- register-read-address pointer maintains its present value, without any reading actually taking place at each rising edge of RCLK. (See Table 3.) Thus, for instance, one or two programmable registers may be read, after which the FIFO may be returned to normal FIFO-array-read/write operation by deasserting LD (to HIGH). To ensure correct operation, the simultaneous reading and writing of a register should be avoided. FIRST LOAD/ RETRANSMIT (FL/RT) FL /RT is a dual-purpose signal. It is one of four input signals which select the grouping mode in which the FIFO operates after being reset; the other three of these input signals are WXI/ WEN2, RXI/REN2, and EMODE. There are four possible grouping modes: standalone, inter- locked paralleled, cascaded ‘master’ or ‘first-load,’ and cascaded ‘slave.’ The designations ‘master’ and ‘slave’ pertain to IDT-compatible depth cascading. Tables 1 and 2 show the signal encodings which select each grouping mode. In standalone or paralleled operation, the FL/ RT pin should be grounded for strict IDT72215B/25B-compatible operation. However, if it is taken HIGH, regardless of the state of the EMODE control input, the FIFO’s internal read-address pointer is reset to address the FIFO’s first physical memory location, without the other usual reset actions being taken; in particular, the FIFO’s internal write-address pointer is unaf- fected. Subsequent read operations may then again read out the same block of data, delimited by the FIFO’s first physical memory location and the current value of the write pointer, as was read out previously. There is no limit on the number of times that a block of data may be retransmitted. The only restrictions are that neither the read-address pointer nor the write-address pointer may ‘wrap around’ and address the FIFO’s first physical memory location a second time during the retransmission process, and that the retransmit facility is unavailable during cascaded opera- tion. In IDT-compatible cascaded operation, FL/ RT is grounded for the ‘master’ or ‘first-load’ FIFO, to distinguish it from the other ‘slave’ FIFOs in the cascade, which must all have their FL/ RT inputs HIGH during a reset operation. (See again Tables 1 and 2.) The cascade will not operate correctly either without any ‘master’ FIFO, or with more than one ‘master’ FIFO. WRITE EXPANSION INPUT/ WRITE ENABLE 2 (WXI/ WEN2) WXI /WEN2 is a dual-purpose signal. It is one of four input signals which select the grouping mode in which the FIFO operates after being reset; the other three of these input signals are FL/ RT, RXI/REN2, and EMODE. There are four possible grouping modes: standalone, inter- BOLD ITALIC = Enhanced Operating Mode LH540215/25 512 x 18/1024 x 18 Synchronous FIFO 18 |
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