LH540215 datasheet(15/48 Pages) SHARP

Part #	LH540215

Description	512 x 18 / 1024 x 18 Synchronous FIFO

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Manufacturer	SHARP [Sharp Corporation]

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Data Inputs

DATA IN (D0 – D17)

Data, programmable-flag-offset values, and

Control-

Register codes are input to the FIFO as 18-bit words on

D0 – D17. Unused bit positions in offset-value and Con-

trol-Register words should be zero-filled.

Control Inputs

RESET (RS)

The FIFO is reset whenever the asynchronous Reset

(RS) input is taken to a LOW state. A reset operation is

required after power-up, before the first write operation

may occur. The state of the FIFO is fully defined after a

reset operation. If the default values which are entered

into the Programmable-Flag-Offset-Value Registers

and

the Control Register by a reset operation are accept-

able, then no device programming is required. A reset

operation initializes the FIFO’s internal read-address and

write-address pointers to the FIFO’s first physical memory

location. The five status flags, FF, PAF, HF, PAE, and EF,

are updated to indicate that the FIFO is completely empty;

thus, the first three of these are reset to HIGH, and the

last two are reset to LOW. The flag-offset values for PAF

and PAE each are initialized to one-eighth of the depth of

a single FIFO, minus one; 63 for a 512-word FIFO, and

127 for a 1024-word FIFO. If

EMODE is not being as-

serted (i.e., if

EMODE is HIGH), all Control Register bits

are initialized to LOW, to configure the FIFO to operate in

the IDT72215B/25B-Compatible Operating Mode. Until a

write operation occurs, the data outputs D0 – D17 all are

LOW whenever OE is LOW.

ENHANCED OPERATING MODE (EMODE)

Whenever EMODE is asserted during a reset op-

eration, Control Register bits 00 – 05 remain HIGH

rather than LOW after the completion of the reset

operation. Thus, EMODE has the effect of activating

all of the Enhanced-Operating-Mode features during

a reset operation. Subsequently, they may be indi-

vidually disabled or re-enabled by changing the set-

ting of Control-Register bits. The behavior of these

Enhanced-Operating-Mode features is described in

Table 5. For permanent Enhanced-Operating-Mode

operation, EMODE must be grounded; dynamic con-

trol of EMODE during system operation is not recom-

mended.

Asserting EMODE during a reset operation also

causes WXI/WEN2 to be configured as WEN2, and

RXI/REN2 to be configured as REN2, to support inter-

locked-paralleled operation of two FIFOs ‘side by

side. (See Figure 27.) Additionally, RXO/EF2 is config-

ured as EF2, which duplicates the EF signal with one

extra RCK cycle delay, in order to provide proper

timing for ‘pipelined’ cascaded operation.

WRITE CLOCK (WCLK)

A rising edge (LOW-to-HIGH transition) of WCLK initi-

ates a FIFO write cycle if LD is HIGH, or a programma-

ble-register write cycle if LD is LOW. The 18 data inputs,

and all input-side synchronous control inputs, must meet

setup and hold times with respect to the rising edge of

WCLK. The input-side status flags are meaningful after

specified time intervals, following a rising edge of WCLK.

Conceptually, the WCLK input receives a free-running,

periodic ‘clock’ waveform, which is used to control other

signals which are edge-sensitive. However, there actually

is not any absolute requirement that the WCLK waveform

must be periodic. An ‘asynchronous’ mode of operation

is in fact possible, if WEN is continuously asserted (that

is, is continuously held LOW), and WCLK receives ape-

riodic ‘clock’ pulses of suitable duration. There likewise is

no requirement that WCLK must have any particular

synchronization relation to the read clock RCLK. These

two clock inputs may in fact receive the same ‘clock’

signal; or they may receive totally-different signals, which

are not synchronized to each other in any way.

WRITE ENABLE (WEN)

Whenever WEN is being asserted (is LOW) and LD is

HIGH, and the FIFO is not full, an 18-bit data word is

loaded into the effective input register for the memory

array at every WCLK rising edge (LOW-to-HIGH transi-

tion). Data words are stored into the two-port memory

array sequentially, regardless of any ongoing read opera-

tion. Whenever WEN is not being asserted (is HIGH), the

input register retains whatever data word it contained

previously, and no new data word gets loaded into the

memory array.

To prevent overrunning the internal FIFO boundaries,

further write operations are inhibited whenever the Full

Flag (FF) is being asserted (is LOW). If a valid read

operation then occurs, upon the completion of that read

cycle FF again goes HIGH after a time tWFF, and another

write operation is allowed to begin whenever WCLK

makes another LOW-to-HIGH transition. Effectively,

WEN is overridden by FF; thus, during normal FIFO

operation, WEN has no effect when the FIFO is full.

In the Enhanced Operating Mode, whenever

EMODE is being asserted (is LOW), WXI/WEN2 func-

tions as WEN2, an additional duplicate (albeit asser-

tive-HIGH) write-enable input, in order to provide

an‘interlocking’ mechanism for reliable synchro-

nization of two paralleled FIFOs. To control writing,

WEN2 is ANDed with WEN; this logic-AND function

(WEN

•••••••

• WEN2) then behaves like WEN in the forego-

ing description.

DESCRIPTION OF SIGNALS AND

OPERATING SEQUENCES (cont’d)

BOLD ITALIC = Enhanced Operating Mode

512 x 18/1024 x 18 Synchronous FIFO

LH540215/25

15

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