Table 5. Control-Register Format

COMMAND

REGISTER

BITS

CODE

VALUE AFTER RESET

FLAG

AFFECTED,

IF ANY

DESCRIPTION

NOTES

EMODE = H

EMODE = L

00

L

LH

–

Deassertion of LD does not

reset the programmable-

register write pointer and

read pointer.

IDT-compatible addressing

of programmable registers.

H

Deassertion of LD resets

the programmable-register

write pointer and read

pointer to address Word 0,

the Programmable-Almost-

Empty-Flag-Offset Register.

The change takes effect

after a valid write operation

or a valid read operation,

respectively, to the memory

array.

Non-ambiguous

addressing of

programmable registers.

01

L

LH

PAE

Set by

↑

↑RCLK, reset by

↑

↑WCLK.

Asynchronous flag

clocking.

H

Set and reset by

↑

↑RCLK.

Synchronous flag clocking.

03, 02

LL

LL

HH

HF

Set by

↑

↑WCLK, reset by

↑

↑RCLK.

Asynchronous flag

clocking.

LH

Set and reset by

↑

↑RCLK.

Synchronous flag clocking

at output port.

HL,

Set and reset by

↑

↑WCLK.

Synchronous flag clocking

at input port.

HH

04

L

L

H

PAF

Set by

↑

↑WCLK, reset by

↑

↑RCLK.

Asynchronous flag

clocking.

H

Set and reset by

↑

↑WCLK.

Synchronous flag clocking.

05

L

LH

–

OE has no effect on an

internal read operation,

apart from disabling the

outputs.

Allows the read-address

pointer to advance even

driving the output bus.

H

Deassertion of OE inhibits

a read operation; whenever

are in the high-Z state, the

read pointer does not

advance.

Inhibits the read-address

pointer from advancing

driving the output bus;

thus, guards against data

loss.

06

L

LL

–

Reserved.

Future use to control depth

cascading and interlocked

paralleling.

H

11, 10,

09, 08, 07

LLLLL

LLLLL

LLLLL

–

Reserved.

Reserved.

NOTES:

1. When EMODE is HIGH, and Control Register bits 00-05 are LOW, the FIFO behaves in a manner functionally equivalent to the

IDT72215B/25B FIFO of similar depth and speed grade. Under these conditions, the

Control Register is not visible or accessible to the ex-

ternal system which includes the FIFO.

2. If EMODE is not asserted (is HIGH), Control Register bits 00-05 remain LOW after a reset operation. However, if EMODE is asserted (is

LOW) during a reset operation, Control Register bits 00-05 are forced HIGH, and remain HIGH until changed. Control Register bits

06-11 are unaffected by EMODE.

BOLD ITALIC = Enhanced Operating Mode

LH540215/25

512 x 18/1024 x 18 Synchronous FIFO

14