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LH540215 Datasheet(PDF) 8 Page - Sharp Corporation

Part # LH540215
Description  512 x 18 / 1024 x 18 Synchronous FIFO
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Manufacturer  SHARP [Sharp Corporation]
Direct Link  http://sharp-world.com/
Logo SHARP - Sharp Corporation

LH540215 Datasheet(HTML) 8 Page - Sharp Corporation

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PIN
NAME
PIN
TYPE
1
DESCRIPTION
WXO/HF
Write
Expansion
Output/
Half-Full Flag
O
This signal is dual-purpose; its functionality is determined during a reset operation
according to the states of the two control inputs WXI/
WEN2 and RXI/REN2. (See
Tables 1 and 2.) In the standalone or paralleled configuration, whenever HF is LOW
the device is more than half full. In IDT-Compatible Operating Mode, HF is
asynchronous;
in the Enhanced Operating Mode, HF may be synchronized
either to WCLK or to RCLK after a reset operation, according to the state of
Control Register bits 02 and 03. (See Table 5.) In the IDT-compatible cascaded
configuration, a pulse is sent from WXO to the WXI input of the next FIFO in the
daisy-chain cascade, whenever the last location in the FIFO is written.
PAE
Programmable
Almost-Empty
Flag
O
When PAE is LOW, the FIFO is ‘almost empty,’ based on the almost-empty-offset
value programmed into the FIFO’s Almost-Empty Offset Register. The default value
of this offset at reset is one-eighth of the total number of words in the FIFO-memory
array, minus one, measured from ‘empty.’ (See Table 4.) In IDT-Compatible
Operating Mode, PAE is asynchronous.
In the Enhanced Operating Mode, PAE
is synchronized to RCLK after a reset operation, according to the state of
Control Register bit 01. (See Table 5.)
EF
Empty Flag
O
When EF is LOW, the FIFO is empty; further advancement of its internal read-
address pointer, and further readout of data words from its internal memory array to
its Data Outputs, are inhibited. When EF is HIGH, the FIFO is not empty. EF is
synchronized to RCLK.
RXO
/EF2
Read
Expansion
Output
O
This signal is dual-purpose; its functionality is determined by the state of the
EMODE control input during a reset operation. (See Tables 1 and 2.) In the IDT-
Compatible Operating Mode, in a cascaded configuration, a pulse is sent from RXO
to the RXI input of the next FIFO in the daisy-chain cascade, whenever the last
location of the FIFO is read.
In the Enhanced Operating Mode, whenever
EMODE is being asserted (LOW), EF2 behaves as an exact duplicate of EF,
but delayed by one full cycle of RCLK with respect to EF.
Q0 – Q17
Data Outputs
O/Z
Data outputs to drive an 18-bit bus.
VCC
Power
V
+5 V power-supply pins.
VSS
Ground
V
0 V ground pins.
NOTE:
1.
I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level
PIN DESCRIPTIONS (cont’d)
BOLD ITALIC = Enhanced Operating Mode
LH540215/25
512 x 18/1024 x 18 Synchronous FIFO
8


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