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LH540203 Datasheet(PDF) 6 Page - Sharp Corporation |
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LH540203 Datasheet(HTML) 6 Page - Sharp Corporation |
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6 / 17 page  OPERATIONAL MODES (cont’d) Depth Cascading Depth cascading is implemented by configuring the required number of LH540203s in depth-cascaded mode. In this arrangement, the FIFOs are connected in a circular fashion, with the Expansion Out output (XO) of each device tied to the Expansion In input (XI) of the next device. One FIFO in the cascade must be designated as the ‘first-load’ device, by tying its First Load input (FL/RT) to ground. All other devices must have their FL/RT inputs tied HIGH. In this mode, W and R signals are shared by all devices, while logic within each LH540203 controls the steering of data. Only one LH540203 is enabled during any given write cycle; thus, the common Data In inputs of all devices are tied together. Likewise, only one LH540203 is enabled during any given read cycle; thus, the common Data Out outputs of all devices are wire- ORed together. In depth-cascaded mode, external logic should be used to generate a composite Full Flag and a composite Empty Flag, by ANDing the FF outputs of all LH540203 devices together and ANDing the EF outputs of all devices together. Since FF and EF are assertive-LOW signals, this ‘ANDing’ actually is implemented using an asser- tive-HIGH physical OR gate. The Half-Full Flag and the Retransmit function are not available in depth-cascaded mode. LH540203 RS RS FF 9 9 RS W FF RS FF 9 9 9 R 9 FL FL EF XI XO FL EF Vcc Vcc XO XO 9 9 XI 540203-19 XI EMPTY FULL EF LH540203 LH540203 DATA IN D0 - D8 DATA OUT Q0 - Q8 Figure 6. FIFO Depth Cascading (6144 × 9) LH540203 CMOS 2048 × 9 Asynchronous FIFO 6 |
Similar Part No. - LH540203 |
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Similar Description - LH540203 |
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