LH540203

CMOS 2048

× 9 Asynchronous FIFO

FEATURES

•• Fast Access Times: 15/20/25/35/50 ns

•• Fast-Fall-Through Time Architecture Based on

CMOS Dual-Port SRAM Technology

•• Input Port and Output Port Have Entirely

Independent Timing

•• Expandable in Width and Depth

•• Full, Half-Full, and Empty Status Flags

•• Data Retransmission Capability

•• TTL-Compatible I/O

•• Pin and Functionally Compatible with Sharp LH5498

and with Am/IDT/MS7203

•• Control Signals Assertive-LOW for Noise Immunity

•• Packages:

28-Pin, 300-mil PDIP

28-Pin, 300-mil SOJ *

32-Pin PLCC

PIN CONNECTIONS

FUNCTIONAL DESCRIPTION

The LH540203 is a FIFO (First-In, First-Out) memory

device, based on fully-static CMOS dual-port SRAM tech-

nology, capable of storing up to 2048 nine-bit words. It

follows the industry-standard architecture and package

pinouts for nine-bit asynchronous FIFOs. Each nine-bit

LH540203 word may consist of a standard eight-bit byte,

together with a parity bit or a block-marking/framing bit.

The input and output ports operate entirely inde-

pendently of each other, unless the LH540203 becomes

either totally full or else totally empty. Data flow at a port

is initiated by asserting either of two asynchronous, as-

sertive-LOW control inputs: Write (W) for data entry at the

input port, or Read (R) for data retrieval at the output port.

Full, Half-Full, and Empty status flags monitor the

extent to which the internal memory has been filled. The

system may make use of these status outputs to avoid

the risk of data loss, which otherwise might occur either

by attempting to write additional words into an already-full

LH540203, or by attempting to read additional words from

an already-empty LH540203. When an LH540203 is

operating in a depth-cascaded configuration, the Half-Full

Flag is not available.

540203-2D

1

2

3

4

5

6

7

8

9

10

11

12

13

14

W

XI

FF

28

27

26

25

24

23

22

21

20

19

18

17

16

15

FL/RT

RS

EF

XO/HF

R

28-PIN PDIP

28-PIN SOJ

*

TOP VIEW

Figure 1. Pin Connections for PDIP and

SOJ * Packages

5

6

7

8

9

10

XI

FF

11

2

3

4

32 31 30

29

28

27

26

25

24

NC

EF

14 15 16

20

19

18

17

FL/RT

RS

23

XO/HF

22

21

12

NC

13

1

540203-3D

32-PIN PLCC

TOP VIEW

NOTE:

Figure 2.

Pin Connections for PLCC Package

* This is a final data sheet; except that all references to the SOJ package have Advance Information status.

1