12V, 8A 1.2MHz

Step-Down Regulator

8

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Pin Description

PIN

NAME

FUNCTION

1, 2, 3, 34,

35, 36

PGND

Power Ground. All PGND pins are internally connected. Connect all PGND pins externally to the power

ground plane.

4

VDL

5V LDO Output. VDL supplies the gate-drive current to the internal MOSFETS, and charges the BST

capacitor. VDL requires at least a 2.2µF ceramic bypass capacitor to PGND.

5–8

IN

Power-Supply Input. Input supply range is from 4.5V to 14V. Bypass with two 10µF and a 0.1µF ceramic

capacitors to PGND. See Figure 1.

9VP

Input of the Internal 5V LDO Regulator. Connect to IN if a 5V supply is not available. Connect to an external

5V supply to disable the internal 5V regulator.

10

VL

3.3V LDO for Internal Chip Supply. Bypass with a 1µF ceramic capacitor to GND.

11

ILIM

LX current-limit trip point. See the Current Limit section for more details.

12

FREQ

Oscillator Frequency Selection. Connect a resistor from FREQ to GND to set the internal oscillator

frequency. See the Frequency Select (FREQ) section for more details.

13, 32

GND

Analog Circuit Ground

14

REFIN

External Reference Input. Connect to an external reference. FB regulates to the voltage applied to REFIN.

Connect REFIN to SS to use the internal 0.6V reference. REFIN is internally pulled to GND when the IC is in

shutdown mode.

15

SS

Soft-Start Input. Connect a capacitor from SS to GND to set the startup time. See the Soft-Start and REFIN

section for details.

16

COMP

Regulator Compensation. Connect the necessary compensation network from COMP to FB. COMP is

internally pulled to GND when the IC is in shutdown mode.

17

FB

Feedback Input. Connect to the center tap of an external resistor-divider from the output to GND to set the

output voltage. See the Compensation Design section for more details.

18

PWRGD

below the UVLO threshold, or the IC is in thermal shutdown.

19

SYNCOUT

Oscillator Output. The SYNCOUT output is 180

° out-of-phase from the internal oscillator to facilitate running

a second regulator out-of-phase to reduce input ripple.

20

SYNC

Synchronization Input. Synchronize to an external clock with a frequency of 250kHz to 1.2MHz. Connect

SYNC to GND to disable the synchronization function.

21

BST

High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.22µF ceramic capacitor.

22–29

LX

Inductor Connection. All LX pins are internally connected together. Connect all LX pins to the switched

side of the inductor. LX is high impedance when the IC is in shutdown mode.

30, 33

N.C.

Not Internally Connected

31

EN

Enable Input. Logic input to enable/disable the MAX8654. Drive EN high to enable the IC. Drive EN low to

place the IC in a low-power shutdown mode.

—EP

Exposed Pad. Connect to a large PGND ground plane to optimize thermal performance. EP is internally

connected to GND and PGND.