SS

SS

SS

FB

t

I

2ms

10 A

C

33 nF

V

0.6 V

´

´

m

=

=

»

(

)

(

)

(

)

UVLO on

UVLO off

UVLO hys

UVLO

V

V

8 V

7 V

R

66.7 k

68.1k

I

15 A

-

-

=

=

=

W »

W

m

(

)

(

)

(

)

(

)

UVLO(max)

UVLO set

UVLO hys

UVLO(on _ min)

UVLO(max)

V

1.25 V

R

R

68.1k

12.6 k

12.7 k

8.0 V

1.25 V

V

V

>

´

=

W

=

W »

W

-

-

TPS40322

www.ti.com

SLUSAF8

– JUNE 2011

(28)

Power Good (PG1, PG2 Pins)

PG1 and PG2 can each be pulled up to BP6 through a 100-k

Ω resistor, or remain not-connected. For sequencing

the start-up of output 1 before output 2, connect PG1 to EN2/SS2; for sequencing the startup of output 2 before

output 1, connect PG2 to EN1/SS1.

Phase Set (PHSET Pin)

The PHSET pin can be connected to ground or connected to the BP6 pin for connections to ground (GND).

UVLO Programming Resistors (R1 and R3)

The UVLO hysteresis level is programmed by R1 with Equation 29 and Equation 30.

(29)

(30)

VDD Bypass Capacitor (C2)

As shown in the ELECTRICAL CHARACTERISTICS table, a 0.1-

µF, 50-V, X7R capacitor has been selected for

VDD bypass.

VBP6 Bypass Capacitor (C18)

Per the TPS40322 datasheet, select a 3.3-

µF (or greater) low ESR capacitor for BP6. For this design a 3.3-µF,

X5R ceramic capacitor was chosen

Schematic

Figure 23 shows the dual output converter schematic for this design example

Copyright

© 2011, Texas Instruments Incorporated

25